Abstract: A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.