Abstract: An electrophoretic display able to operate on a reduced power supply includes a display panel and a driving circuit electrically connected to the display panel. The display panel includes a plurality of first electrophoretic particles and a plurality of second electrophoretic particles. The driving circuit is configured to provide a balance signal to the display panel during a balance period, provide a mixed signal to the display panel during a mixing period, and provide a driving signal to the display panel during a coloring period. The balance period, the mixing period, and the coloring period are sequential in time, and a preset time interval is between each of the periods.

Abstract: An electrophoretic display able to operate on a reduced power supply includes a display panel and a driving circuit electrically connected to the display panel. The display panel includes a plurality of first electrophoretic particles and a plurality of second electrophoretic particles. The driving circuit is configured to provide a balance signal to the display panel during a balance period, provide a mixed signal to the display panel during a mixing period, and provide a driving signal to the display panel during a coloring period. The balance period, the mixing period, and the coloring period are sequential in time, and a preset time interval is between each of the periods.

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.

Abstract: A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level.

Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

Abstract: Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device.

Abstract: A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.

Abstract: An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

Abstract: A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein.

Abstract: A slew rate control circuit is disclosed. An output impedance buffer and a slew rate buffer are coupled in parallel. An edge detector detects an input signal to accordingly control the output impedance buffer and the slew rate buffer, such that the input signal passes through the slew rate buffer during a rising or falling time period, and the input signal only passes through the output impedance buffer during a stable time period, thereby conforming to specification requirements for the slew rate and the output impedance at the same time.

Abstract: One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal.

Abstract: A slew rate control circuit is disclosed. An output impedance buffer and a slew rate buffer are coupled in parallel. An edge detector detects an input signal to accordingly control the output impedance buffer and the slew rate buffer, such that the input signal passes through the slew rate buffer during a rising or falling time period, and the input signal only passes through the output impedance buffer during a stable time period, thereby conforming to specification requirements for the slew rate and the output impedance at the same time.

Abstract: A writing circuit for a phase change memory is provided. The writing circuit comprises a driving current generating circuit, a first switch device, a first memory cell and a second switch device. The driving current generating circuit provides a writing current to the first memory cell. The first switch device is coupled to the driving current generating circuit. The first memory cell is coupled between the first switch device and the second switch device. The second switch device is coupled between the first memory cell and a ground, wherein when the driving current generating circuit outputs the writing current to the first memory cell, the second switch device is turned on after the first switch device has been turned on for a first predetermined time period.

Abstract: An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the number of times is large than a predetermined number.

Abstract: An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.