Patents by Inventor Liem T. Tran
Liem T. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6037646Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.Type: GrantFiled: May 30, 1997Date of Patent: March 14, 2000Assignee: TRW Inc.Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
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Patent number: 5930636Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.Type: GrantFiled: May 13, 1996Date of Patent: July 27, 1999Assignee: TRW Inc.Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
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Patent number: 5892248Abstract: A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.Type: GrantFiled: September 30, 1996Date of Patent: April 6, 1999Assignee: TRW Inc.Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
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Patent number: 5840612Abstract: A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.Type: GrantFiled: August 14, 1997Date of Patent: November 24, 1998Assignee: TRW Inc.Inventors: Aaron K. Oki, Dwight C. Streit, Donald K. Umemoto, Liem T. Tran
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Patent number: 5736417Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.Type: GrantFiled: May 13, 1996Date of Patent: April 7, 1998Assignee: TRW Inc.Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
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Patent number: 5631477Abstract: An InAlAs/InGaAlAs heterojunction bipolar transistor that includes a constant quaternary InGaAlAs collector layer. Graded InGaAlAs collector layers are provided on each side of the quaternary collector layer to minimize transitions through the constant collector layer. The InAlAs/InGaAlAs HBT may also include one or more of a graded InGaAlAs emitter-base transition region, a graded-doping InGaAs base layer, and a graded-composition InGaAlAs base layer.Type: GrantFiled: June 2, 1995Date of Patent: May 20, 1997Assignee: TRW Inc.Inventors: Dwight C. Streit, Aaron K. Oki, Liem T. Tran
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Patent number: 5068705Abstract: Vertical AlGaAs heterojunction bipolar transistors and GaAs junction field effect transistors are fabricated on a single gallium arsenide (GaAs) substrate to form an integrated circuit structure. The integration of these devices is made possible by a novel method of fabricating heterojunction inverted transistor integrated logic (HI2L) transistors with emitter reigons on the bottom (contacted through the substrate) while simultaneously forming the JFET structure with no additional processing steps. An ion implant technique is employed which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. A zinc diffusion is used to form the bipolar P type ohmic contact regions and JFET gate regions in one operation. Bipolar collector and JFET source and drain metallization patterns are formed simultaneously followed by the simultaneous formation of bipolar base and JFET metallization patterns.Type: GrantFiled: February 13, 1991Date of Patent: November 26, 1991Assignee: Texas Instruments IncorporatedInventor: Liem T. Tran
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Patent number: 5013682Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.Type: GrantFiled: June 30, 1989Date of Patent: May 7, 1991Assignee: Texas Instruments IncorporatedInventors: Donald L. Plumton, Liem T. Tran, Hung-Dah Shih
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Patent number: 4868633Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small, isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectively grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirrors being the sidewalls of the vertical structures.Type: GrantFiled: October 22, 1986Date of Patent: September 19, 1989Assignee: Texas Instruments IncorporatedInventors: Donald L. Plumton, Liem T. Tran, Hung-Dah Shih
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Patent number: 4743569Abstract: A two step rapid thermal anneal (RTA) has been studied for activating Be implanted GaAs, where a short duration high temperature step is used to electrically activate the Be followed by a longer low temperature anneal for lattice re-growth. PN diodes show a substantial reduction in reverse diode leakage current after the lower temperature second step anneal, when compared to a single step RTA or to furnace annealing (FA). For low energy Be implants, no difference in electrical activation between the single step and the two step anneal is observed. Raman studies demonstrate that residual substrate impurities and high Be concentrations inhibit restoration of single crystal lattice characteristics after RTA. Lattice quality is also shown not to limit diode characteristics in the RTA material.Type: GrantFiled: April 20, 1987Date of Patent: May 10, 1988Assignee: Texas Instruments IncorporatedInventors: Donald L. Plumton, Liem T. Tran, Walter M. Duncan