Abstract: A plurality of cells of a flash memory are tested to determine if they need to be refreshed. The cells are read and a plurality of different sensing ratios are used to determine if any of the cells need to be refreshed. Any cells that are determined to need refreshing are refreshed. The cells are read using only a single constant gate voltage.

Abstract: A plurality of cells of a flash memory are tested to determine if they need to be refreshed. The cells are read and a plurality of different sensing ratios are used to determine if any of the cells need to be refreshed. Any cells that are determined to need refreshing are refreshed. The cells are read using only a single constant gate voltage.

Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.

Abstract: In a method to verify a mask for a mask ROM, a serial of random codes that are exclusive to each other are implanted into a plurality of wafers manufactured by a same process with the mask or a plurality of die regions in a single wafer manufactured by a same process with the mask, and then the test results derived from the implanted wafers or die regions are compared to determine if the mask is defective.

Abstract: A method for defining a dummy pattern around an alignment mark on a wafer. First, a wafer having an alignment area with an alignment mark is provided. Thereafter, lithography is performed on the wafer by a mask to define a first dummy pattern around the alignment mark in the alignment area. The mask includes a first dummy pattern area, with a first pattern to mask the alignment mark and a second pattern to define the first dummy pattern, and a second dummy pattern area, with a third pattern to define a second dummy pattern around the first dummy pattern.

Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.

Abstract: A method of deleting repeating defects having no effect on product yield of a wafer so that true defects on the wafer are more readily found. A wafer having a plurality of dies thereon is provided. The wafer is scanned to find any repeating defects. If the repeating defects have no effect on the product yield, the area around the repeating defects is marked out as “don't care” region. Another wafer scanning operation to find the true defects is subsequently conducted by scanning the region outside the “don't care” region.

Abstract: A method of manufacturing MOS transistors is disclosed. The method includes a step of depositing a shield layer on a silicon substrate prior to forming source/drain regions. The shield layer is formed to cover a gate electrode and a field oxide layer (or shallow trench isolation) on a silicon substrate with a uniform thickness. Then, the silicon substrate is heavily implanted. The implanting energy is controlled to prevent ions from penetrating the shield layer at the sidewall region of the gate electrode. After removing the shield layer, the silicon substrate is processed with lightly implantation. In this way, a MOS transistor with LDD is formed with less manufacturing steps.

Abstract: A bond pad of a semiconductor device and a process for fabricating the same are provided. On a semiconductor base is formed a plurality of disconnected insulation blocks that are defined by a plurality of channels. The disconnected insulation blocks are arranged in a grid or helix form. A barrier layer is formed over the disconnected insulation blocks and the semiconductor base. A conductive layer is formed over the disconnected insulation blocks to fill the channels, such that a topography of the conductive layer is similar to that of the underlying structure.