Abstract: A method of eliminating a defective bonding wire is provided, including moving a bonding member from a first region of a carrier to a second region of the carrier if the bonding wire of the bonding member is defective, and cooperatively operating a movement member and the bonding member so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier, thereby auto-debugging the bonding member and improving the production efficiency.

Abstract: A method for fabricating an electronic package, including the steps of: providing a substrate having a plurality of electronic elements and a plurality of separation portions formed between the electronic elements, wherein each of the electronic elements has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; forming at least an opening in each of the separation portions from a side corresponding to the inactive surfaces of the electronic elements, wherein the at least an opening does not penetrate the separation portion; forming an encapsulant in the opening; and singulating the electronic elements along the opening from a side corresponding to the active surfaces of the electronic elements. As such, each of the electronic elements has a side surface adjacent to and connecting the active and inactive surfaces of the electronic element and the side surface is partially covered by the encapsulant for protection.

Abstract: A package substrate is provided, which includes: a body having opposite first and second surfaces, each having adjacent first and second regions defined thereon; first and second circuit layers formed on the first and second surfaces of the body, respectively; a first insulating layer formed on the first surface of the body and having a plurality of first openings formed in the first insulating layer and positioned in the first and second regions; and a second insulating layer formed on the second surface of the body and having a plurality of second openings formed in the second insulating layer and positioned in the second region. Further, at least a third opening is formed in the second insulating layer and positioned in the first region to reduce the volume of the second insulating layer, thereby facilitating even distribution of thermal stresses through the first and second insulating layers during thermal cycling and hence preventing warpage of the package substrate.

Abstract: A method of eliminating a defective bonding wire is provided, including moving a bonding member from a first region of a carrier to a second region of the carrier if the bonding wire of the bonding member is defective, and cooperatively operating a movement member and the bonding member so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier, thereby auto-debugging the bonding member and improving the production efficiency.

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes providing a carrier board; forming a plurality of metal bumps on the carrier board; covering on the carrier board a resist layer having openings for exposure of the metal bumps, the openings being smaller than the metal bumps in width such that a metal layer is formed in the openings, the metal layer having extension circuits and extension pads and bonding pads formed on respective ends of the extension circuits; removing the resist layer; electrically connecting at least one semiconductor chip to the bonding pads; forming an encapsulant on the carrier board to encapsulate the semiconductor chip; and removing the carrier board and the metal bumps to expose the metal layer.

Abstract: A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as to allow a flow rate of an encapsulating resin flowing through the gap during a molding process to be reduced by the blocking surfaces, such that different portions of the encapsulating resin respectively flowing above, in and below the die pad can have substantially the same flow rate, thereby preventing bonding wires from being deformed to cause short circuit and avoiding formation of voids. A semiconductor package with the lead frame structure is also provided.

Abstract: A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as to allow a flow rate of an encapsulating resin flowing through the gap during a molding process to be reduced by the blocking surfaces, such that different portions of the encapsulating resin respectively flowing above, in and below the die pad can have substantially the same flow rate, thereby preventing bonding wires from being deformed to cause short circuit and avoiding formation of voids. A semiconductor package with the lead frame structure is also provided.

Abstract: A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is electrically connected to the lead frame via bonding wires bonded to the bonding layer. During a molding process for fabricating an encapsulant to encapsulate the chip, the bonding wires and a portion of the lead frame, the embossed structure makes the bonding layer become uneven and thus increases the contact area and adhesion between the bonding layer and the encapsulant, so as to prevent cracks of the bonding wires and improve the electrical performances and molding reliability.

Abstract: A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is electrically connected to the lead frame via bonding wires bonded to the bonding layer. During a molding process for fabricating an encapsulant to encapsulate the chip, the bonding wires and a portion of the lead frame, the embossed structure makes the bonding layer become uneven and thus increases the contact area and adhesion between the bonding layer and the encapsulant, so as to prevent cracks of the bonding wires and improve the electrical performances and molding reliability.

Abstract: A package structure having tapering support bars and leads. The package structure has at least a lead frame, a die, a plurality of conductive wires and an encapsulating plastic body. The lead frame has a first surface and has at least a package unit. The package unit has a die pad, a plurality of leads and a plurality of support bars. The die pad is positioned in the middle. The leads and support bars are distributed around the periphery of the package unit. In addition, the width of the leads and support bars decreases gradually from a location close to the die pad towards the peripheral region. The leads and support bars have a rectangular or trapezoidal cross-section. A die is bonded on the surface of the die pad and the die is electrically connected to the leads on the lead frame via a plurality of conductive wires. Plastic material such as epoxy resin encloses the die, the conductive wires and the first surface of the lead frame.

Abstract: A semiconductor package for chip with testing contact pad includes a chip, a plurality of leads, at least a flow-conducting plate, and a molding compound. The chip has an active surface provided with a plurality of functional contact pads and at least a testing contact pad. The leads are bonded onto the active surface of the chip and respectively connected to the functional contact pads through a plurality of functional wires. The flow-conducting plate is connected to the testing contact pad through at least a testing wire. The molding compound encapsulates the chip, the leads, the flow-conducting plate, the functional contact pads, and the testing contact pads.

Abstract: A quad flat non-leaded package structure for housing a sensor. The package includes a die pad, a plurality of leads, a die, a plurality of bonding wires, a packaging plastic body and a lid cover. A plurality of supporters are formed near the edges on the backside of the die pad. The plurality of leads is positioned at a well-defined distance away from the four sides of the die pad. The packaging plastic body is formed on the upper surface near the peripheral section of the leads. The space between the die pad and the leads is filled by the packaging plastic material but the bottom section of the leads and the bottom section of the supporters on the backside of the die pad are exposed. The die is attached to the upper surface of the die pad and is electrically connected to the leads using the bonding wires. The lid cover is placed over the packaging plastic body.

Abstract: A semiconductor package for chip with testing contact pad comprises a chip, a plurality of leads, at least a flow-conducting plate, and a molding compound. The chip has an active surface provided with a plurality of functional contact pads and at least a testing contact pad. The leads are bonded onto the active surface of the chip and respectively connected to the functional contact pads through a plurality of functional wires. The flow-conducting plate is connected to the testing contact pad through at least a testing wire. The molding compound encapsulates the chip, the leads, the flow-conducting plate, the functional contact pads, and the testing contact pads.

Abstract: The present invention provides a package comprising a lead frame, which has a die pad and a plurality of leads located at the peripheral of the die pad. An image sensor chip has an active surface and a corresponding back surface. A plurality of bonding pads are on the active surface. A plurality of leads are electrically connected from the bonding pads to the inner leads. The image sensor chip, the die pads and the inner leads are encapsulated with a transparent molding material. A cavity is formed on a surface of the transparent molding material corresponding to the active surface. The area of the cavity, which is large enough just to cover the chip of the image sensor, has a smooth surface after a polishing process.

Abstract: A quad flat non-leaded package structure for housing a sensor. The package includes a die pad, a plurality of leads, a die, a plurality of bonding wires, a packaging plastic body and a lid cover. A plurality of supporters are formed near the edges on the backside of the die pad. The plurality of leads is positioned at a well-defined distance away from the four sides of the die pad. The packaging plastic body is formed on the upper surface near the peripheral section of the leads. The space between the die pad and the leads is filled by the packaging plastic material but the bottom section of the leads and the bottom section of the supporters on the backside of the die pad are exposed. The die is attached to the upper surface of the die pad and is electrically connected to the leads using the bonding wires. The lid cover is placed over the packaging plastic body.