Abstract: An electronic device includes a substrate, a first silicon transistor, a second silicon transistor and a first oxide semiconductor transistor. The first silicon transistor, the second silicon transistor and the first oxide semiconductor transistor are disposed on the substrate. The first silicon transistor has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second silicon transistor has a first terminal electrically connected to the second terminal of the first silicon transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first silicon transistor. The first oxide semiconductor transistor has a first terminal electrically connected to the first terminal of the second silicon transistor. Wherein, a voltage value of the first voltage level is greater than a voltage value of the second voltage level.

Abstract: An auxiliary positioning system includes an ultra-wideband (UWB) element, and a service management and orchestration (SMO) apparatus and a near-real time ran intelligent controller (Near-RT RIC) connected with each other, wherein the SMO apparatus includes a non-real time ran intelligent controller (Non-RT RIC). The UWB element is connected to a second application disposed at at least one of the SMO apparatus, the Near-RT RIC and the Non-RT RIC through a first application. The UWB element is configured to output positioning information of a user device to the second application through the first application.

Abstract: A system for expansion of open radio access network includes a service management and orchestration (SMO) apparatus and a near-real time ran intelligent controller (Near-RT RIC) connected with each other, wherein the SMO apparatus includes a non-real-time ran intelligent controller (Non-RT RIC). Each of the SMO apparatus, the Near-RT RIC and the Non-RT RIC includes a first decoder, and at least one of the SMO apparatus, the Near-RT RIC and the Non-RT RIC includes a second decoder. The first decoder is configured to decode a first packet of a first communication protocol, the second decoder is configured to decode a second packet of a second communication protocol, and the first communication protocol is different from the second communication protocol.

Abstract: A hybrid cluster system includes at least one computing node for providing computing resources and at least one storage node for providing storage resources. A specification of the at least one computing node is identical to a specification of the at least one storage node.

Abstract: A server switch system includes a switch unit and a field-programmable gate array (FPGA) unit. The switch unit includes a first switch interface for receiving the first data and sending the second data, and a second switch interface for sending the third data and receiving the fourth data. The switch unit is used to generate the third data according to the first data, and generate the second data according to the fourth data. The FPGA unit includes an FPGA interface coupled to the second switch interface for receiving the third data from the switch unit and sending the fourth data to the switch unit.

Abstract: The present disclosure relates to a method for testing connectivity. The method is applied to an electronic equipment which is disposed include two test units (e.g. network interface controller, RJ-45 connector) and a network transformer. The test unit couple to the network transformer so that can send a high frequency test signal or a low frequency test signal to the network transformer respectively. When the test unit receives a low frequency response signal, it means correspond internal circuitry of the network transformer does not have a open circuit fault. When the test unit does not receive a high frequency response signal, it means correspond pins of the network transformer does not have a short circuit fault.

Abstract: The present disclosure relates to a method for testing connectivity. The method is applied to an electronic equipment which is disposed include two test units (e.g. network interface controller, RJ-45 connector) and a network transformer. The test unit couple to the network transformer so that can send a high frequency test signal or a low frequency test signal to the network transformer respectively. When the test unit receives a low frequency response signal, it means correspond internal circuitry of the network transformer does not have a open circuit fault. When the test unit does not receive a high frequency response signal, it means correspond pins of the network transformer does not have a short circuit fault.

Abstract: The present disclosure provides a testing apparatus for executing a test program, to perform a first test on a circuit component on a circuit board and a second test on the circuit board. The testing apparatus includes a first module, a second module, and a signal transmission line that connects the two. The first module includes a control unit, a signal generation unit, a signal processing unit, a signal expansion unit, and a power supply unit. The control unit generates a first control signal or a second control signal. The signal generation unit generates a current signal or a voltage signal. The signal processing unit generates a numerical signal. The signal expansion unit generates a second data signal. The power supply unit generates a working voltage. The second module includes a test address assignment unit that assigns an address and a signal isolation unit that performs noise immunization process.

Abstract: The present disclosure provides a testing apparatus for executing a test program, to perform a first test on a circuit component on a circuit board and a second test on the circuit board. The testing apparatus includes a first module, a second module, and a signal transmission line that connects the two. The first module includes a control unit, a signal generation unit, a signal processing unit, a signal expansion unit, and a power supply unit. The control unit generates a first control signal or a second control signal. The signal generation unit generates a current signal or a voltage signal. The signal processing unit generates a numerical signal. The signal expansion unit generates a second data signal. The power supply unit generates a working voltage. The second module includes a test address assignment unit that assigns an address and a signal isolation unit that performs noise immunization process.

Abstract: A testing method for a unit under test is provided. At least one unit under test is electrically connected to a testing machine. The testing machine creates a test script and executes the test script, so as to perform a non-operating system (OS) test and an OS test on the unit under test, and the testing machine is capable of combining the testing results, so a testing process is simplified, a test time is shortened, and test accuracy is improved.

Abstract: A multi-chip test system and a method thereof utilize a Complex Programmable Logic Device (CPLD) to be connected in series to multiple chips having a Joint Test Action Group (JTAG) interface for function inspection. The test system includes a device to-be-tested and a control device. The device to-be-tested includes multiple chips, a CPLD, and a second JTAG interface. Each of the chips has a first JTAG interface. The CPLD is coupled to the chips through the first JTAG interfaces. The second JTAG interface is connected to the CPLD. The control device is connected to the second JTAG interface and used for sending a switching instruction to the CPLD. In the test method, firstly, a switching instruction is received to select a chip to-be-tested; then, a test signal is sent to the chip to-be-tested according to the chip to-be-tested; and the chip to-be-tested transfers a test result back to a CPLD according to the test signal.