Abstract: A plurality of memory cells of a semiconductor memory device of the present invention are classified into a plurality of column groups. Drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line. Source electrodes of the memory cells belonging to the same column group are connected to the same second bit line. A gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via a word line. An amplifier amplifies a potential of the selected second bit line.