Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. one of the cells which is coupled to one of the first input pads and one of the second input pads is turned on, and a current flowing through the turned-on cell is measured.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A method includes receiving a workpiece. The workpiece includes a first dummy gate, a second dummy gate adjacent the first dummy gate, a first gate spacer disposed along sidewalls of the first dummy gate, and a second gate spacer disposed along sidewalls of the second dummy gate. The method further includes removing the first dummy gate and the second dummy gate to form a first gate trench and a second gate trench, respectively, enlarging the first gate trench and the second gate trench, forming a first metal gate structure in the enlarged first gate trench, and forming a second metal gate structure in the enlarged second gate trench. The enlarged second gate trench is wider than the enlarged first gate trench.

Abstract: A semiconductor device includes: a first memory array with a first side; a second memory array with a second side that faces the first side; and a well pickup region between the first memory array along the first side and the second memory array along the second side, the well pickup region having a first region and a second region each with an n-well tap cell and a middle region with a p-well tap cell between the first region and the second region, wherein a first edge region of the first region is placed along the first side of the first memory array region and a second edge region of the second region is placed along the second side of the second memory array region; wherein the p-well tap cell includes a contiguous OD region for providing reverse bias to P-N junctions in the first and second memory array regions.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming a first gate structure over the substrate and crossing the first semiconductor fin; forming a second gate structure over the substrate and crossing the second semiconductor fin; forming a first gate spacer on a sidewall of the first gate structure; and forming a second gate spacer on a sidewall of the second gate structure, wherein in a top view, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure, and an inner sidewall of the first gate spacer in contact with the first gate structure is misaligned with an inner sidewall of the second gate spacer in contact with the second gate structure.

Abstract: The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

Abstract: Semiconductor structures and methods for fabricating semiconductor structures are provided. A semiconductor structure includes a first fin extending in an X-direction and a second fin parallel to the first fin and distanced from the first fin in a Y-direction perpendicular to the X-direction. Each fin is formed with a first device area and a second device area aligned in the X-direction; an isolation region disposed between the fins; an isolation structure disposed between the device areas in each fin; and an isolation layer disposed under the fins. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device area from the second device area in each fin.

Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature.

Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.

Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

Abstract: A semiconductor structure includes a first transistor and a second transistor, and a dielectric structure separating the first transistor from the second transistor. The first transistor includes a first gate structure and the second transistor includes a second gate structure. The dielectric structure includes a first portion sandwiched between the first gate structure and the second gate structure along a first direction, and a second portion protruding from the first portion along a second direction perpendicular to the first direction. The first portion has a first width and the second portion has a second width less than the first width, the first width and the second width being along the first direction, and the first portion has a first height and the second portion has a second height less than the first height.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.