Patents by Inventor Liesbeth Witters

Liesbeth Witters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361268
    Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 23, 2019
    Assignee: IMEC VZW
    Inventors: Kurt Wostyn, Hans Mertens, Liesbeth Witters, Andriy Hikavyy, Naoto Horiguchi
  • Patent number: 10340139
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 2, 2019
    Assignee: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Patent number: 10269929
    Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 23, 2019
    Assignee: IMEC VZW
    Inventors: Kurt Wostyn, Liesbeth Witters, Hans Mertens
  • Publication number: 20190013395
    Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 10, 2019
    Applicant: IMEC VZW
    Inventors: Liesbeth Witters, Kurt Wostyn
  • Patent number: 10090393
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 2, 2018
    Assignee: IMEC VZW
    Inventors: Steven Demuynck, Zheng Tao, Boon Teik Chan, Liesbeth Witters, Marc Schaekers, Antony Premkumar Peter, Silvia Armini
  • Publication number: 20180254321
    Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.
    Type: Application
    Filed: February 28, 2018
    Publication date: September 6, 2018
    Applicant: IMEC VZW
    Inventors: Kurt Wostyn, Hans Mertens, Liesbeth Witters, Andriy Hikavyy, Naoto Horiguchi
  • Publication number: 20180166558
    Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 14, 2018
    Applicant: IMEC VZW
    Inventors: Kurt Wostyn, Liesbeth Witters, Hans Mertens
  • Patent number: 9972622
    Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 15, 2018
    Assignee: IMEC VZW
    Inventors: Liesbeth Witters, Anabela Veloso
  • Patent number: 9842777
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 12, 2017
    Assignee: IMEC vzw
    Inventors: Liesbeth Witters, Kurt Wostyn
  • Publication number: 20170141199
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.
    Type: Application
    Filed: November 8, 2016
    Publication date: May 18, 2017
    Applicant: IMEC VZW
    Inventors: Steven Demuynck, Zheng Tao, Boon Teik Chan, Liesbeth Witters, Marc Schaekers, Antony Premkumar Peter, Silvia Armini
  • Patent number: 9633891
    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 25, 2017
    Assignee: IMEC VZW
    Inventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters
  • Publication number: 20170040168
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 9, 2017
    Applicant: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Publication number: 20170025314
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 26, 2017
    Inventors: Liesbeth Witters, Kurt Wostyn
  • Patent number: 9502415
    Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 22, 2016
    Assignee: IMEC VZW
    Inventors: Roger Loo, Jerome Mitard, Liesbeth Witters
  • Publication number: 20160336317
    Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.
    Type: Application
    Filed: May 12, 2016
    Publication date: November 17, 2016
    Applicant: IMEC VZW
    Inventors: Liesbeth Witters, Anabela Veloso
  • Patent number: 9476143
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 25, 2016
    Assignee: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Patent number: 9478544
    Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 25, 2016
    Assignee: IMEC vzw
    Inventors: Jerome Mitard, Roger Loo, Liesbeth Witters
  • Patent number: 9343329
    Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 17, 2016
    Assignee: IMEC VZW
    Inventors: Alexey Milenin, Liesbeth Witters
  • Publication number: 20160126131
    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 5, 2016
    Applicant: IMEC VZW
    Inventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters
  • Patent number: 9299563
    Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 29, 2016
    Assignees: IMEC VZW, Samsung Electronics Co. Ltd.
    Inventors: Seung Hun Lee, Liesbeth Witters, Roger Loo