Abstract: A thinned semiconductor substrate is provided. The front end of line portion on the front side includes conductive structures of the thinned substrate, which may be contacted by connections through the substrate. An opening is etched from the back to be filled with a conductive material. The bottom of the opening overlaps the end surface of the conductive structure to be contacted and further overlaps a portion of semiconductor material of the substrate. Etching of the opening continues beyond the end surface into the semiconductor portion(s), to create cavities. A first dielectric layer is formed on the sidewalls and bottom of the opening. The cavities are filled with the material of the first layer. This material is removed except in the cavities. The dielectric-filled cavities inhibit the formation of shorts between the through-connection obtained by filling the opening and the semiconductor material of the substrate.

Abstract: A semiconductor product is provided. The semiconductor product comprises a first wafer (21) comprising a first active pad array (21a), and at least a second wafer (22) comprising at least a second active pad array (22a). In this context, the first wafer (21) and the at least one second wafer (22) are bonded together. In addition to this, the first wafer (21) and/or the at least one second wafer (22) comprises a transition area (23) being directly adjacent to the first active pad array (21a) and/or the at least one second active pad array (22a).

Abstract: A layer of semiconductor devices is produced on the frontside of a crystalline semiconductor substrate, in regions separated by dielectric-filled cavities formed previously. Additional layers are then formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the backside. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface. After this, an anisotropic etch is performed to remove additional material of the first substrate. The in-plane dimensions of the device regions separated by the dielectric-filled cavities are specified so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in the cavities, before it can reach the devices on the frontside.

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate.

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate.

Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.