Patents by Inventor Lieven Mark Koenraad VANDERSYPEN

Lieven Mark Koenraad VANDERSYPEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11721725
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: August 8, 2023
    Assignees: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11721748
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: August 8, 2023
    Assignees: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11721723
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 8, 2023
    Assignees: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Publication number: 20230036699
    Abstract: A method of controlling coupling of at least two quantum dots in a quantum dot array is described, wherein the method comprises: determining virtual gates for the quantum dots based on first crosstalk contributions of physical gates to dot potentials of quantum dots in the quantum dot array, a virtual gate voltage defining a linear combination of physical gate voltages to be applied to the physical gates for controlling at least one dot potential of a quantum dot or for controlling a coupling of at least two quantum dots in the quantum dot array, while at least partially compensating dot potential crosstalk due to the first crosstalk contributions; determining second crosstalk contributions of the virtual gates to a coupling between one or more pairs of quantum dots in the quantum dot array, the determining including determining partial derivatives of couplings between pairs of quantum dots in the quantum dot array with respect to the virtual gate voltages; determining enhanced virtual gates for the quantum d
    Type: Application
    Filed: January 21, 2021
    Publication date: February 2, 2023
    Applicant: Technische Universiteit Delft
    Inventors: Cornelis Jacobus VAN DIEPEN, Tzu-Kan HSIAO, Lieven Mark Koenraad VANDERSYPEN
  • Publication number: 20220181445
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Applicants: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11322591
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Publication number: 20210296473
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Applicants: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Publication number: 20210280676
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 9, 2021
    Applicants: Intel Corporation, Technishce Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11063138
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11038021
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 10872956
    Abstract: Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot circuit. The quantum dot circuit comprises a channel (10), first gate electrodes (14a-14e) that extend over locations along the edge of the channel to create potentials barriers defining the potentials well therebetween, as well as second gate electrodes (16a-16d) adjacent to potential wells, for controlling depths of the successive electrical potential wells between the potential barriers. First, channel currents are measured in a pre-scan of bias voltages of the first gates for controlling the potential barriers. The result is used to set their bias levels in, a scan over a two-dimensional range of combinations of bias voltages on the second gates for controlling the depths.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 22, 2020
    Assignees: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, Technische Universiteit Delft
    Inventors: Pieter Thijs Eendebak, Timothy Alexander Baart, Lieven Mark Koenraad Vandersypen
  • Publication number: 20200176569
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Application
    Filed: June 24, 2017
    Publication date: June 4, 2020
    Applicants: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Publication number: 20200161455
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
    Type: Application
    Filed: June 24, 2017
    Publication date: May 21, 2020
    Applicants: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Publication number: 20200135864
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Application
    Filed: June 24, 2017
    Publication date: April 30, 2020
    Applicants: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Publication number: 20200127096
    Abstract: Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot circuit. The quantum dot circuit comprises a channel (10), first gate electrodes (14a-14e) that extend over locations along the edge of the channel to create potentials barriers defining the potentials well therebetween, as well as second gate electrodes (16a-16d) adjacent to potential wells, for controlling depths of the successive electrical potential wells between the potential barriers. First, channel currents are measured in a pre-scan of bias voltages of the first gates for controlling the potential barriers. The result is used to set their bias levels in, a scan over a two-dimensional range of combinations of bias voltages on the second gates for controlling the depths.
    Type: Application
    Filed: March 6, 2017
    Publication date: April 23, 2020
    Applicant: Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO
    Inventors: Pieter Thijs EENDEBAK, Timothy Alexander BAART, Lieven Mark Koenraad VANDERSYPEN