Abstract: Aspects of the technology described herein related to controlling, using control circuitry, modulation circuitry to modulate and delay first ultrasound data generated by first ultrasound transducers positioned at a first azimuthal position of an ultrasound transducer array of an ultrasound device and second ultrasound data generated by second ultrasound transducers positioned at a second azimuthal position of the ultrasound transducer array of the ultrasound device, such that the first ultrasound data is delayed by a first delay amount and the second ultrasound data is delayed by a second delay amount that is different from the first delay amount. The first and second ultrasound data received from the modulation circuitry may be filtered and summed. The ultrasound transducer array, the control circuitry, the modulation circuitry, the filtering circuitry, and the summing circuitry may be integrated onto a semiconductor chip or one or more semiconductor chips packaged together.

Abstract: Aspects of the technology described herein related to controlling, using control circuitry, modulation circuitry to modulate and delay first ultrasound data generated by first ultrasound transducers positioned at a first azimuthal position of an ultrasound transducer array of an ultrasound device and second ultrasound data generated by second ultrasound transducers positioned at a second azimuthal position of the ultrasound transducer array of the ultrasound device, such that the first ultrasound data is delayed by a first delay amount and the second ultrasound data is delayed by a second delay amount that is different from the first delay amount. The first and second ultrasound data received from the modulation circuitry may be filtered and summed. The ultrasound transducer array, the control circuitry, the modulation circuitry, the filtering circuitry, and the summing circuitry may be integrated onto a semiconductor chip or one or more semiconductor chips packaged together.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Aspects of the technology described herein related to controlling, using control circuitry, modulation circuitry to modulate and delay first ultrasound data generated by first ultrasound transducers positioned at a first azimuthal position of an ultrasound transducer array of an ultrasound device and second ultrasound data generated by second ultrasound transducers positioned at a second azimuthal position of the ultrasound transducer array of the ultrasound device, such that the first ultrasound data is delayed by a first delay amount and the second ultrasound data is delayed by a second delay amount that is different from the first delay amount. The first and second ultrasound data received from the modulation circuitry may be filtered and summed. The ultrasound transducer array, the control circuitry, the modulation circuitry, the filtering circuitry, and the summing circuitry may be integrated onto a semiconductor chip or one or more semiconductor chips packaged together.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Circuitry for ultrasound devices is described. A multi-level pulser is described, which can support time-domain and spatial apodization. The multi-level pulser may be controlled through a software-defined waveform generator. In response to the execution of a computer code, the waveform generator may access master segments from a memory, and generate a stream of packets directed to pulsing circuits. The stream of packets may be serialized. A plurality of decoding circuits may modulate the streams of packets to obtain spatial apodization.

Abstract: Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.

Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

Abstract: Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.

Abstract: Managing access to an external memory in a computing system comprising one or more cores includes: receiving memory requests to access a memory at a memory controller coupled to at least one of the cores; assigning, by the memory controller, respective priorities to the memory requests, the priorities being based on priority configuration information; providing access, by the memory controller, to the memory based on the memory requests according to the assigned priorities. Messages are received at the memory controller to modify the priority configuration information.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.

Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions and is configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first dimension ordering policy, and from the intermediate processor core to a destination processor core. The first dimension ordering policy specifies an ordering of the dimensions of the interconnection network when routing data through the interconnection network.

Abstract: A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.