Abstract: The present invention provides a method for implementing EDA data parametric modeling, comprising: constructing three mapping tables when performing attribute parameterization operations on a single or batch commands; performing parameterization on a single or batch commands; and affecting all entities parameterized by parameters when modifying parameter values. The method realizes batch modification of model data, group control of parameters, supporting Redo/Undo.

Abstract: A DXF data import modeling method, a system, and a medium. The present invention provides a DXF data import modeling method, used for solving the problems that an existing DXF data import operation is complex and the modeling effect cannot be visually displayed. The method comprises: reading DXF data and constructing an entity database; constructing a rendering database; creating layers; constructing a mapping relation table between a layer ID and an entity ID; constructing a layer configuration information table; monitoring configuration information in the layer configuration information table, and synchronously updating rendering data correspondingly; and when the configuration information is completed, ending the import modeling process.

Abstract: The invention provides a method for extracting and configuring resistance and inductance (RL) parameters based on a fast multipole method, which comprises following steps: proposing brand-new basis functions, dividing surface currents using centroid-midpoint basis functions, configuring an accurate impedance model, and proposing a brand-new method and preconditions for using FMM; the CM basis function introduced by the present invention can convert traditional vector bit integration operations based on edges into scalar bit integration operations based on surface elements, and the new integration calculation method is easier to operate and faster in calculation speed. The accurate impedance model enables the present invention to carry out broadband simulation from low frequency to high frequency; the corresponding use of FMM only needs to be based on the surface elements of edges. It is easier to configure the fast multipole method.

Abstract: The present invention discloses a method for accelerated solving of large sparse matrix, system and storage medium thereof, which falls into the technical field of electromagnetic field computation. In view of the problem that solving of the current large sparse matrix is slow and not accurate enough, the present invention provides a method for accelerated solving of large sparse matrix, comprising: restoring connection relationships between port nodes of an initial finite element matrix, and obtaining restored second-order finite element matrix; converting the second-order finite element matrix to an undirected graph; decomposing the undirected graph, and selecting optimal decomposition via an evaluation function; renumbering nodes of the second-order finite element matrix according to the renumbered nodes and generating a new final finite element matrix; and solving the final finite element matrix.

Abstract: A circuit simulation optimization method, device, computer device and storage medium, wherein the circuit simulation optimization method comprises: acquiring initial design parameters of a design circuit, and calculating an initial value of an S-parameter based on the initial design parameters of the design circuit; judging whether the design circuit is qualified according to design requirements according to the initial value of the S-parameter value and a preset S-parameter threshold; when the design circuit is not qualified according to the design requirements, calculating a derivative of an object function corresponding to the S-parameter at the initial design parameters; and searching for a point of a smallest possible value of the object function corresponding to the S-parameter in a preset interval of the initial design parameters according to the derivative.

Abstract: The present invention discloses a chip packaging power distribution network electromagnetic modeling method and system, belongs to the technical field of chip packaging.

Abstract: The present invention is applicable to the field of layout design and simulation, and provides a parameterized cell data updating method and apparatus, a computer device and a storage medium. The method comprises: determining a target basic primitive according to the state identifier of the basic primitive (S302), wherein the basic primitive is a minimum primitive forming a parameterized cell, the state identifier is used for identifying whether the configuration parameter of the primitive is consistent with attribute data, and the configuration parameter is used for specifying the attribute data of the primitive; updating the attribute data of the target basic primitive according to the configuration parameter (S304); and iteratively updating the attribute data of the parameterized cell according to the attribute data of the target basic primitive (S306).

Abstract: A method for real-time extraction of on-chip simulation information including acquiring simulation job information, and analyzing the simulation job information to obtain option and parameter information; and acquiring index information from a simulation project according to the option and the parameter information, and formatting the index information to obtain a simulation result. According to said method, key information of a simulation result is extracted in real time by performing text scanning and pattern analysis on a log file during a simulation process, so that a user can conveniently learn about the progress situation of the current simulation task at any time, and determine to continue or terminate the task at any time according to the current state and result situation, thereby more flexibly controlling a flow according to an actual situation, simplifying operations, increasing design efficiency, and compensating for the disadvantages of traditional simulation methods.

Abstract: A multilevel distributed parallel computing method for integrated circuit board simulation, belonging to the technical field of integrated circuit simulation, includes following steps: S100, calculating number of nodes; S200, allocating tasks; S300, calculating and solving; and S40, judging convergence. By dynamically paralleling multiple computers, the present invention can maximize utilization of computing resources, improve simulation efficiency, and finally achieve a purpose of shortening design cycle. And in the simulation process, through the dynamic result analysis method, frequency points that need to be solved can be actually found, and accurate full-band results with the least number of solutions is completed.

Abstract: A method for real-time extraction of on-chip simulation information including acquiring simulation job information, and analyzing the simulation job information to obtain option and parameter information; and acquiring index information from a simulation project according to the option and the parameter information, and formatting the index information to obtain a simulation result. According to said method, key information of a simulation result is extracted in real time by performing text scanning and pattern analysis on a log file during a simulation process, so that a user can conveniently learn about the progress situation of the current simulation task at any time, and determine to continue or terminate the task at any time according to the current state and result situation, thereby more flexibly controlling a flow according to an actual situation, simplifying operations, increasing design efficiency, and compensating for the disadvantages of traditional simulation methods.

Abstract: A method for reconstructing physical connection relationships of general EDA model layouts comprising: separately establishing interconnection relationships between stack layers in an EDA model, connection relationships of graphics on each stack layer, and connection relationships of graphics on interconnected stack layers; summarizing the connection relationships established, and then establishing connection relationships of all graphics of an overall EDA model; and separately establishing physical connection relationships of interconnected graphics in each group to obtain physical connection relationships of the overall EDA model layout.