Abstract: In a vital sign sensor of the present invention, an antenna assembly radiates an oscillation signal generated by a SIL oscillator to an object in a form of a wireless signal and receives a reflected signal from the object, and the reflected signal can have the SIL oscillator injection-locked. The wireless signal radiated from the antenna assembly is transmitted to a demodulator for demodulation such that the vital signs of the object can be obtained. Additionally, an isolator of the antenna assembly is provided to prevent the SIL oscillator from receiving a clutter reflected from the demodulator and an environment where the demodulator is placed. As a result, the clutter can't influence the vital sign detection of the object.

Abstract: In a vital sign sensor of the present invention, an antenna assembly radiates an oscillation signal generated by a SIL oscillator to an object in a form of a wireless signal and receives a reflected signal from the object, and the reflected signal can have the SIL oscillator injection-locked. The wireless signal radiated from the antenna assembly is transmitted to a demodulator for demodulation such that the vital signs of the object can be obtained. Additionally, an isolator of the antenna assembly is provided to prevent the SIL oscillator from receiving a clutter reflected from the demodulator and an environment where the demodulator is placed. As a result, the clutter can't influence the vital sign detection of the object.

Abstract: Disclosed is a communications device that monitors the status of its communications links. When more than one communications link is available, an “appropriate” link is selected for use by an application running on the device. The links are continually monitored, and, as circumstances change, the link selection can also change. In some embodiments, a link is “appropriate” when it is available to transfer data and when it satisfies certain “hard” rules set by the application or by a user of the communications device. Some embodiments monitor the behaviour of the communications device and of its user and capture that behaviour in “soft” rules that are applied when selecting an appropriate link and when the hard rules leave the choice open. When multiple links transmit on the same frequency, they may be supported “virtually simultaneously” by time-slicing the actual data transmissions. Unneeded links may be shut down to save battery power.

Abstract: A method, apparatus, and electronic device for regulating communication are disclosed. A first radio 304 may execute a coordination communication operation using a coordination protocol. A coordinator layer 230 may determine an optimum protocol for a communication operation based on the coordination communication operation. A second radio 302 may use the optimum protocol.

Abstract: A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage.

Abstract: A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage.

Abstract: A first and second capacitor plate are provided (101 and 102). Each capacitor plate has an opening disposed therethrough with the second capacitor plate being disposed substantially opposite the first capacitor plate. A first electrically conductive path interface is then disposed (103) in one of these openings as is at least a second electrically conductive path interface (104).

Abstract: A method, apparatus, and electronic device for achieving simultaneous communication between multiple protocols are disclosed. The method may include receiving with a telecommunication device a first message on a first communications network using a first communications protocol; simultaneously receiving with the telecommunication device a second message on a second communications network using a second communications protocol; assigning a first priority to the first message; assigning a second priority to the second message; and processing the first message and the second message in an order based on the first priority and the second priority.

Abstract: A first and second capacitor plate are provided (101 and 102). Each capacitor plate has an opening disposed therethrough with the second capacitor plate being disposed substantially opposite the first capacitor plate. A first electrically conductive path interface is then disposed (103) in one of these openings as is at least a second electrically conductive path interface (104).

Abstract: An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

Abstract: An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

Abstract: A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a package 20 comprising a mount surface 14 to which dice 61 and 65 are mounted, and a bond pad surface 25 defining at least a first die area 27 and a second die area 29, wherein the second die area 29 is different in form from the first die area 27.

Abstract: An embodiment of a current-carrying structure (100) includes a first electrically conductive layer (110) and a second electrically conductive layer (120). The second electrically conductive layer is in contact with the first electrically conductive layer along substantially the entire length of the first electrically conductive layer. The second electrically conductive layer is above the first electrically conductive layer. A non-electrically conductive layer (130) is in contact with the first electrically conductive layer and the second electrically conductive layer. A current travels simultaneously through the first electrically conductive layer and the second electrically conductive layer.

Abstract: A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a package 20 comprising a mount surface 14 to which dice 61 and 65 are mounted, and a bond pad surface 25 defining at least a first die area 27 and a second die area 29, wherein the second die area 29 is different in form from the first die area 27.

Abstract: An embodiment of a current-carrying structure (100) includes a first electrically conductive layer (110) and a second electrically conductive layer (120). The second electrically conductive layer is in contact with the first electrically conductive layer along substantially the entire length of the first electrically conductive layer. The second electrically conductive layer is above the first electrically conductive layer. A non-electrically conductive layer (130) is in contact with the first electrically conductive layer and the second electrically conductive layer. A current travels simultaneously through the first electrically conductive layer and the second electrically conductive layer.

Abstract: A bonding structure (10) is formed between a first component (12) and a second component (11) to form a semiconductor device. The bonding structure (10) comprises a bump (24) that has a pedestal region (22) and a crown region (23). The crown region (23) is anchored into a well region (13) of a conductive material (16) that is formed on the second component (11).

Abstract: A process for using removable Z-axis anisotropically conductive adhesive material (21) which includes water, a matrix resin (23), and conductive spheres (22). The material (21) is suitable for providing temporary contact between electronic devices. In one embodiment, the material (21) is used to temporarily bond a semiconductor wafer (11) to a probe substrate (12) for wafer-level burn-in.

Abstract: A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

Abstract: Apparatus for mounting a semiconductor device chip and making electrical connections thereto is disclosed. A semiconductor device chip has its backside connected to the surface of a substrate, and its upper surface includes a plurality of electrical pads across the entire surface thereof. A translator chip having a plurality of first electrical contacts disposed generally across the interior portion thereof are in electrical contact with the semiconductor device chip electrical pads, and a plurality of second electrical contacts disposed generally around the perimeter of the translator chip are electrically connected with the electrical terminals in the substrate to which the chip is attached. Heat may be removed from the semiconductor device chip through its backside via cooling channels in the substrate.