Patents by Inventor LIH-YIH CHIOU
LIH-YIH CHIOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11600319Abstract: A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.Type: GrantFiled: June 18, 2021Date of Patent: March 7, 2023Assignee: National Cheng Kung UniversityInventors: Lih-Yih Chiou, Yu-Wei Lin, Wei-Shuo Ling
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Publication number: 20220262426Abstract: A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.Type: ApplicationFiled: June 18, 2021Publication date: August 18, 2022Applicant: National Cheng Kung UniversityInventors: Lih-Yih Chiou, Yu-Wei Lin, Wei-Shuo Ling
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Patent number: 10964384Abstract: A method for controlling a resistive random access memory (ReRAM) is proposed. The method calculates a number of a bit value of a data when the data is to be written to the resistive random access memory. Each bit of the data is flipped and the data is written to the ReRAM if the number of the bit value is greater than a half of a length of the data. The data as it original is written to the ReRAM if the number of the bit value is less than a half of the length of the data.Type: GrantFiled: August 23, 2018Date of Patent: March 30, 2021Assignee: Industrial Technology Research InstituteInventors: Tsai-Kan Chien, Lih-Yih Chiou, Jing-Cian Lin
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Publication number: 20180366187Abstract: A method for controlling a resistive random access memory (ReRAM) is proposed. The method calculates a number of a bit value of a data when the data is to be written to the resistive random access memory. Each bit of the data is flipped and the data is written to the ReRAM if the number of the bit value is greater than a half of a length of the data. The data as it original is written to the ReRAM if the number of the bit value is less than a half of the length of the data.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Applicant: Industrial Technology Research InstituteInventors: Tsai-Kan Chien, Lih-Yih Chiou, Jing-Cian Lin
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Patent number: 10089182Abstract: An energy-efficient nonvolatile microprocessor includes a processing core, a nonvolatile flip-flop array, a set of nonvolatile interconnections, and a store-enable register. When a power source is recovered to a stable state, the processing core determines whether data of nonvolatile registers is not transmitted before power-off. If yes, the processing core executes programmable recovery entry decision to avoid recovery failures for different applications. The processing core has plural system states divided into programmer visible states and programmer invisible states. The nonvolatile interconnections are connected between the processing core and the nonvolatile flip-flop array. When the power source is unstable, the processing core only stores the programmer visible states into the nonvolatile flip-flop array and, at the same time, only stores the system states of the peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.Type: GrantFiled: May 23, 2016Date of Patent: October 2, 2018Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Lih-Yih Chiou, Tsai-Kan Chien, Chang-Chia Lee
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Patent number: 9996641Abstract: A thermal simulation device for an integrated circuit according to the disclosure comprises a thermal analysis unit and a mesh size analysis unit. The thermal analysis unit performs a thermal analysis of the integrated circuit to obtain temperatures of the center point and boundary of each function block. The mesh size analysis unit determines the cell number in the mesh of each function block. The thermal analysis unit computes a temperature of the center point and boundary of each cell in every function block according to the temperatures of the boundary of each function block.Type: GrantFiled: January 8, 2016Date of Patent: June 12, 2018Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Lih-Yih Chiou, Liang-Ying Lu
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Patent number: 9734909Abstract: A non-volatile static random access memory has an operating mode, a data backup mode and a data restore mode. The non-volatile static random access memory includes a memory cell and a power saving module. The memory cell includes a latch, a set of latch switch units, a set of backup memory units, a set of backup activation units, a backup setting unit and a driving signal transmission unit. The power saving module includes a control switch unit, a backup determination unit and a restore switch unit. When backup data is different from data stored in the latch, a backup driving signal is generated by a node voltage of the backup memory units and outputted to a backup determination unit, which drives the backup setting unit to turn on according to the backup driving signal, so as to change the backup data in the backup memory units and ensure correct backup.Type: GrantFiled: March 17, 2016Date of Patent: August 15, 2017Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Lih-Yih Chiou, Tsai-Kan Chien, Yi-Sung Tsou
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Publication number: 20170213588Abstract: A memory comprised of a plurality of single port SRAM memory cells, each driven by two word lines in an asynchronous manner has a hold mode, a read mode and a write mode. Each of the single port SRAM memory cells includes a first write switch, a second write switch and a latch. The first write switch is electrically connected to a first word line and is turned on by a first turn-on signal transmitted by the first word line. The second write switch is electrically connected to a second word line and is turned on by a second turn-on signal transmitted by the second word line. When the memory is in the write mode, the second write switch is turned on by the second turn-on signal having a delay with respect to the first turn-on signal, thereby blocking the pseudo read of the unselected memory cell.Type: ApplicationFiled: September 14, 2016Publication date: July 27, 2017Inventors: LIH-YIH CHIOU, CHI-RAY HUANG
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Patent number: 9715922Abstract: A memory comprised of a plurality of single port SRAM memory cells, each driven by two word lines in an asynchronous manner has a hold mode, a read mode and a write mode. Each of the single port SRAM memory cells includes a first write switch, a second write switch and a latch. The first write switch is electrically connected to a first word line and is turned on by a first turn-on signal transmitted by the first word line. The second write switch is electrically connected to a second word line and is turned on by a second turn-on signal transmitted by the second word line. When the memory is in the write mode, the second write switch is turned on by the second turn-on signal having a delay with respect to the first turn-on signal, thereby blocking the pseudo read of the unselected memory cell.Type: GrantFiled: September 14, 2016Date of Patent: July 25, 2017Assignee: National Cheng Kung UniversityInventors: Lih-Yih Chiou, Chi-Ray Huang
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Patent number: 9646695Abstract: A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.Type: GrantFiled: March 7, 2016Date of Patent: May 9, 2017Assignee: National Cheng Kung UniversityInventors: Lih-Yih Chiou, Tsai-Kan Chien
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Publication number: 20160364298Abstract: An energy-efficient nonvolatile microprocessor includes a processing core, a nonvolatile flip-flop array, a set of nonvolatile interconnections, and a store-enable register. When a power source is recovered to a stable state, the processing core determines whether data of nonvolatile registers is not transmitted before power-off. If yes, the processing core executes programmable recovery entry decision to avoid recovery failures for different applications. The processing core has plural system states divided into programmer visible states and programmer invisible states. The nonvolatile interconnections are connected between the processing core and the nonvolatile flip-flop array. When the power source is unstable, the processing core only stores the programmer visible states into the nonvolatile flip-flop array and, at the same time, only stores the system states of the peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.Type: ApplicationFiled: May 23, 2016Publication date: December 15, 2016Inventors: Lih-Yih CHIOU, Tsai-Kan CHIEN, Chang-Chia LEE
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Publication number: 20160283149Abstract: A non-volatile static random access memory has an operating mode, a data backup mode and a data restore mode. The non-volatile static random access memory includes a memory cell and a power saving module. The memory cell includes a latch, a set of latch switch units, a set of backup memory units, a set of backup activation units, a backup setting unit and a driving signal transmission unit. The power saving module includes a control switch unit, a backup determination unit and a restore switch unit. When backup data is different from data stored in the latch, a backup driving signal is generated by a node voltage of the backup memory units and outputted to a backup determination unit, which drives the backup setting unit to turn on according to the backup driving signal, so as to change the backup data in the backup memory units and ensure correct backup.Type: ApplicationFiled: March 17, 2016Publication date: September 29, 2016Inventors: LIH-YIH CHIOU, TSAI-KAN CHIEN, YI-SUNG TSOU
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Publication number: 20160284408Abstract: A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.Type: ApplicationFiled: March 7, 2016Publication date: September 29, 2016Inventors: LIH-YIH CHIOU, TSAI-KAN CHIEN
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Patent number: 9448122Abstract: A multi-point temperature sensing method for integrated circuit chips and a system of the same are revealed. The system includes at least one slave temperature sensor embedded at preset positions for measuring temperature of a block and a master temperature sensor embedded in an integrated circuit chip and electrically connected to each slave temperature sensor. Variations of the slave temperature sensor induced by variations of process, voltage and temperature are corrected by the master temperature sensor. Thus the area the temperature sensors required on the integrated circuit chip is dramatically reduced and the stability of the temperature control system is improved. The problem of conventional System-on-a-Chip that only a limited number of temperature sensors could be used due to the area they occupied can be solved.Type: GrantFiled: October 4, 2013Date of Patent: September 20, 2016Assignee: National Cheng Kung UniversityInventors: Soon-Jyh Chang, Guan-Ying Huang, Kuen-Jong Lee, Wen-Yu Su, Chung-Ho Chen, Lih-Yih Chiou, Chih-Hung Kuo, Chien-Hung Tsai, Chia-Min Lin
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Publication number: 20160203863Abstract: A resistive random access memory (ReRAM) and a method for controlling the ReRAM are proposed. The method detects a temperature of the ReRAM and set a reference resistance of a sense amplifier of the ReRAM according to the temperature. In addition, the method adapts to temperature fluctuation by switching operating mode based on the temperature of the ReRAM to enhance the reliability of the ReRAM. The control method may include a self-adaptive write mechanism, which takes write errors and data retention errors under high temperature into consideration at the same time. The control method may include a self-adaptive error correcting code mechanism, which determines the number of write errors according to Write-and-Verify (WAV) of writing and chooses the ECC algorithm. The control method may include a programmable WAV mechanism, programmably dividing N steps of WAV into two parts, so as to facilitate a memory write speed.Type: ApplicationFiled: July 22, 2015Publication date: July 14, 2016Inventors: Tsai-Kan Chien, Lih-Yih Chiou, Jing-Cian Lin
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Publication number: 20160203246Abstract: A thermal simulation device for an integrated circuit according to the disclosure comprises a thermal analysis unit and a mesh size analysis unit. The thermal analysis unit performs a thermal analysis of the integrated circuit to obtain temperatures of the center point and boundary of each function block. The mesh size analysis unit determines the cell number in the mesh of each function block. The thermal analysis unit computes a temperature of the center point and boundary of each cell in every function block according to the temperatures of the boundary of each function block.Type: ApplicationFiled: January 8, 2016Publication date: July 14, 2016Inventors: Lih-Yih CHIOU, Liang-Ying LU
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Patent number: 9123436Abstract: An adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) is revealed. The system includes a power supply unit, a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of SRAM, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal. The DVR monitor cell consists of a DRV monitor circuit mounted with a plurality of memory cells, a reset signal generating circuit for resetting the DRV monitor circuit, and an adaptive variation control circuit that generates noise bias according to leakage current to adjust reaction speed of the DRV monitor circuit correspondingly.Type: GrantFiled: July 18, 2014Date of Patent: September 1, 2015Assignee: National Cheng Kung UniversityInventors: Lih-Yih Chiou, Chi-Ray Huang, Kuan-Lin Wu
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Patent number: 9094002Abstract: An in situ pulse-based delay variation monitor that predicts timing errors caused by process and environmental variations is revealed. The monitor includes a sequential storage device having a mater storage device and a slave storage device, a transition detector that is electrically connected to a node set on an electrical connection pathway from a master storage device to the slave storage device, and a warning signal generator electrically connected to the transition detector. The transition detector receives output of the master storage device to form a warning area by delay buffer, and generates a pulse width output correspondingly according to transition of the data input. Thus the warning signal generator generates a warning signal according to logic action at the pulse width and the clock input when the data input reaches the warning area. Thereby timing errors caused by static process variations and dynamic environmental variations are predicted.Type: GrantFiled: November 1, 2013Date of Patent: July 28, 2015Assignee: National Cheng Kung UniversityInventors: Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu
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Publication number: 20150133790Abstract: A gait analysis device cooperated with a running exercise apparatus comprises a plurality of infrared emitting units, a plurality of infrared receiving units, a plurality of supporting units and a processing unit. An end of each of the infrared emitting units is covered by an opaque element. The infrared receiving units and the infrared emitting units are disposed in a staggered arrangement. The infrared receiving units and the infrared emitting units are disposed to the supporting units. The processing unit is coupled with the infrared receiving units. A running exercise apparatus is also disclosed. The gait analysis device is capable of decreasing the interference of the infrared light and thus increasing the accuracy of the gait analysis.Type: ApplicationFiled: March 6, 2014Publication date: May 14, 2015Applicant: NATIONAL CHENG KUNG UNIVERSITYInventors: Hung-Ta CHIU, Lih-Yih CHIOU, Ming-You HSU, Pei-Wei JI
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Publication number: 20150092477Abstract: An adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) is revealed. The system includes a power supply unit, a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of SRAM, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal. The DVR monitor cell consists of a DRV monitor circuit mounted with a plurality of memory cells, a reset signal generating circuit for resetting the DRV monitor circuit, and an adaptive variation control circuit that generates noise bias according to leakage current to adjust reaction speed of the DRV monitor circuit correspondingly.Type: ApplicationFiled: July 18, 2014Publication date: April 2, 2015Inventors: LIH-YIH CHIOU, CHI-RAY HUANG, KUAN-LIN WU