Abstract: A MOS-based active pixel sensor cell utilizes the parasitic bipolar action of the cell to produce a horizontal current in lieu of the vertical image current associated with conventional bipolar-based active pixel sensor cells. Image data is collected during an integration period by applying a negative voltage to the gate of the MOS transistor which is sufficient to reverse-bias both the source/body and drain/body junctions. Following this, the image data is read out by raising the gate voltage such that the source/body junction remains reverse-biased, and the drain/body junction becomes forward-biased. Under these bias conditions, an amplified horizontal image current flows from the source, through the body, and out of the drain.

Abstract: A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub is formed surrounding the P+ body region in order to enhance avalanche breakdown. Thus the epitaxial layer resistivity can be decreased to reduce device on-resistance, while the desired breakdown voltage is also achieved. The on-resistance is further reduced by adding a pre-initial oxidation implant, i.e. phosphorous for an N channel device or boron for a P channel device. This forms a more heavily doped JFET or pinch region at the bottom of the trench and in the upper portion of the drift region. This N JFET region (which is P doped for a P channel device) is more heavily doped than the underlying epitaxial layer and surrounds the trench bottom, thus reducing on-resistance by increasing local doping concentration where otherwise a parasitic JFET would be present.

Abstract: A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

Abstract: The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the present invention, a negative voltage is applied to the gate of the trench transistor with its drain grounded and its source floating. A leakage current flowing between the gate and drain is measured as a function of the voltage applied to the gate. A transistor whose gate-drain leakage current exceeds a predetermined value at a specified gate voltage is deemed to be defective. In another embodiment of the present invention, the gate-drain leakage current is measured as described above and monitored over time. Charge accumulated near the gate-drain interface due to defects in the interface results in the gate-drain leakage current taking a longer period of time to fall off to its steady state value.