Abstract: An error correction code circuit includes a first error correction code circuit configured to generate correction data and a first correction check bit according to received source data and a source check bit corresponding to the received source data, a second error correction code circuit connected to the first error correction code circuit, and configured to, according to the correction data and at least one of the first correction check bit or the source check bit, determine whether the correction data is wrong and generate a second correction check bit, and a comparison circuit connected between the first error correction code circuit and the second error correction code circuit, and configured to compare the first correction check bit with the second correction check bit and determine whether the first correction check bit is wrong.

Abstract: A mycovirus-induced gene silencing vector and a construction method and an application thereof are provided. A nucleotide sequence of the mycovirus-induced gene silencing vector is shown in SEQ ID NO: 2, and construction method for the mycovirus-induced gene silencing vector includes: (1) connecting three single-stranded circular DNA molecules DNA-A, DNA-B and DNA-C of the mycovirus FgGMTV1/HB58 in series and introducing them into a same vector to construct a recombinant vector; and (2) carrying out a deletion mutation on a coding protein p26 of the DNA-C molecule in the recombinant vector to obtain the mycovirus-induced gene silencing vector.

Abstract: A mycovirus-induced gene silencing vector and a construction method and an application thereof are provided. A nucleotide sequence of the mycovirus-induced gene silencing vector is shown in SEQ ID NO: 2, and construction method for the mycovirus-induced gene silencing vector includes: (1) connecting three single-stranded circular DNA molecules DNA-A, DNA-B and DNA-C of the mycovirus FgGMTV1/HB58 in series and introducing them into a same vector to construct a recombinant vector; and (2) carrying out a deletion mutation on a coding protein p26 of the DNA-C molecule in the recombinant vector to obtain the mycovirus-induced gene silencing vector.

Abstract: A data access method includes obtaining a data access request for M storage devices, M being an integer greater than or equal to 2, determining a target access mode for the M storage devices based on the data access request, and performing data access on the storage devices based on access control signals matching the target access mode for the storage devices. The target access mode includes a first access mode and a second access mode. Access security and/or access speed generated when the data access is performed on the storage devices in the first access mode is different from access security and/or access speed generated in the second access mode.

Abstract: A dynamic loading system of an off-chip non-volatile memory based on virtual mapping includes the off-chip non-volatile memory, an on-chip memory, an on-chip mapping device, a memory access controller, and an off-chip memory. The on-chip mapping device is configured to construct a mapping relationship between a logical partition and a physical partition of the on-chip memory. The memory access controller is configured to parse a memory access of a system into an access to the logical partition, configure a prediction algorithm of data loading, and send a memory loading request to the off-chip memory loading device. The off-chip memory loading device is configured to construct a mapping relationship between a program partition of the off-chip non-volatile memory and the physical partition of the on-chip memory.

Abstract: A virtualized SoC bus system comprises a plurality of distributor modules, a plurality of system exchanger modules, and a plurality of arbiter modules, wherein the distributor modules distribute data requests sent by hosts to different system exchanger modules, the system exchanger modules analyze the data requests of the hosts and distribute the data requests to different arbiter modules according to analysis results, and each arbiter module pools the data requests sent by the plurality of system exchanger modules to an output interface and sends same to a device to which the arbiter module is connected. The present invention further provides a configuration method for the virtualized SoC bus system. The execution efficiency of virtual machines in the virtualized system can be improved, and reliable bus isolation is provided for the virtual machines, so that the mutual interference among the virtual machines is reduced, and the stability of the system is improved.

Abstract: An error correction code circuit includes a first error correction code circuit configured to generate correction data and a first correction check bit according to received source data and a source check bit corresponding to the received source data, a second error correction code circuit connected to the first error correction code circuit, and configured to, according to the correction data and at least one of the first correction check bit or the source check bit, determine whether the correction data is wrong and generate a second correction check bit, and a comparison circuit connected between the first error correction code circuit and the second error correction code circuit, and configured to compare the first correction check bit with the second correction check bit and determine whether the first correction check bit is wrong.

Abstract: A multi-chip interconnection system includes a plurality of chips. A chip of the plurality of chips includes an extend serial peripheral interface (XSPI) master terminal, a data transmission terminal, an XSPI slave terminal, and a data reception terminal. The XSPI master terminal includes an advanced extensible interface (AXI) slave interface. The data transmission terminal accesses the AXI slave interface via an AXI bus. The XSPI slave terminal includes an AXI master interface. The data reception terminal accesses the AXI master interface via the AXI bus. An XSPI master terminal of a chip is connected to an XSPI slave terminal of another chip via an XSPI bus. The XSPI master terminal of the chip performs encoding on AXI information of the data transmission terminal of the chip received via the AXI bus and transmits encoded AXI information to the XSPI slave terminal of the another chip via the XSPI bus.

Abstract: A fault management system for functional safety of an automotive grade chip includes: an out-of-chip system and an automotive-grade chip, where the automotive-grade chip includes a processor, a system controller, a system configuration module, a fault management device, and an on-chip function module; and the fault management device is configured with a fault classification management model.

Abstract: An image distortion correction system includes an image data acquirer configured to receive image data from a camera, crop an image of the image data according to cropping control information generated by an image corrector, and stores the image data of the cropped image into a memory; the image corrector configured to retrieve the image data of the cropped image from the memory, correct the cropped image, and send the image data of the corrected image to a display driver for display; a display follower configured to generate a display line-field synchronization signal and send the display line-field synchronization signal to the display driver; the display driver; and the memory.

Abstract: A dynamic loading system of an off-chip non-volatile memory based on virtual mapping includes the off-chip non-volatile memory, an on-chip memory, an on-chip mapping device, a memory access controller, and an off-chip memory. The on-chip mapping device is configured to construct a mapping relationship between a logical partition and a physical partition of the on-chip memory. The memory access controller is configured to parse a memory access of a system into an access to the logical partition, configure a prediction algorithm of data loading, and send a memory loading request to the off-chip memory loading device. The off-chip memory loading device is configured to construct a mapping relationship between a program partition of the off-chip non-volatile memory and the physical partition of the on-chip memory.

Abstract: A hierarchical system firewall, comprising a root security manager, secondary security managers, a firewall controller, and firewalls. The root security manager designates a secondary security manager and allocates a system resource for each domain cluster, and provides firewall configuration schemes between the domain clusters. The secondary security managers add domain identifiers for hosts and devices of domain clusters, and provides a firewall configuration scheme for each domain. The firewall controller adds domain cluster identifiers for the hosts and devices in the system, and adds identification for the secondary security managers; allocates domain identification for a host and a device of a current domain cluster; and configures access permissions for the firewall of each device in the current domain cluster. The firewalls perform permissions control for access to a current device by hosts from different domains or different domain clusters.

Abstract: A virtualized SoC bus system comprises a plurality of distributor modules, a plurality of system exchanger modules, and a plurality of arbiter modules, wherein the distributor modules distribute data requests sent by hosts to different system exchanger modules, the system exchanger modules analyze the data requests of the hosts and distribute the data requests to different arbiter modules according to analysis results, and each arbiter module pools the data requests sent by the plurality of system exchanger modules to an output interface and sends same to a device to which the arbiter module is connected. The present invention further provides a configuration method for the virtualized SoC bus system. The execution efficiency of virtual machines in the virtualized system can be improved, and reliable bus isolation is provided for the virtual machines, so that the mutual interference among the virtual machines is reduced, and the stability of the system is improved.

Abstract: A method of generating a super-resolution image from a single frame of image data includes using a processor to retrieve query patches of image data from a memory, determining a search range for each patch, and generating super-resolution image data corresponding to each patch based upon the search range.

Abstract: A system including a memory configured to store a plurality of initial frames of a video signal and a plurality of motion vectors; and a multi-frame interpolator coupled to the memory and including a first output port and a second output port, the frame interpolator configured to generate a first output frame and a second output frame from the initial frames and the motion vectors, to output the first output frame through the first output port and output the second output frame through the second output port.