Abstract: A server comprises a cabinet, a computing node and a plurality of hard disk assemblies. The cabinet is provided with a computing node accommodating slot and a plurality of hard disk accommodating slots. The computing node is assembled in the computing node accommodating slot, wherein the computing node is not provided with any hard disk. The hard disk assemblies are respectively assembled in the hard disk accommodating slots, wherein each of the hard disk assemblies has a plurality of hard disks, and the plurality of hard disk is electrically connected to the computing node.

Abstract: The invention provides server including a casing. The casing has back panel area. The back panel area is located at air outlet of the server. Package substrate, up HDD back panel and down HDD back panel are horizontally disposed on the back panel area. Motherboard of the server is communicatively connected to the package substrate via first connector. The package substrate is communicatively connected to the up HDD back panel via second connector. The up HDD back panel is communicatively connected to the down HDD back panel via third connector. The server of the invention has high dense storage devices, very high space utilization, and innovative heat dissipation channels design. The server has high configuration flexibility and expansibility, can be operated in a simple manner, and can support apparatus that are power-consuming and operating in standby mode.

Abstract: A method for managing two baseboard management controllers comprises connecting to a first baseboard management controller, sending an instruction to the first baseboard management controller, determining whether the instruction comprises a bridge parameter, when the instruction comprises the bridge parameter, sending the instruction to a second baseboard management controller through a bus, generating a response signal by the second baseboard management controller, and receiving the response signal by the first baseboard management controller and sending the response signal to an administration interface; otherwise, executing a corresponding operation according to the instruction by the first baseboard management controller and sending an operation result to the administration interface.

Abstract: A method for managing two baseboard management controllers comprises connecting to a first baseboard management controller, sending an instruction to the first baseboard management controller, determining whether the instruction comprises a bridge parameter, when the instruction comprises the bridge parameter, sending the instruction to a second baseboard management controller through a bus, generating a response signal by the second baseboard management controller, and receiving the response signal by the first baseboard management controller and sending the response signal to an administration interface; otherwise, executing a corresponding operation according to the instruction by the first baseboard management controller and sending an operation result to the administration interface.

Abstract: A control system includes a first expander board and a second expander board. The first expander board selects a first data segment from a first data signal according to a first clock signal. The second expander board is electrically connected to the first expander board. The second expander board is configured to receive the first data segment and the first clock signal of the first expander board. The second expander board selects a second data segment from a second data signal according to a second clock signal and sequentially outputs the first data segment and the second data segment. The sequentially output form of the first data segment and the second data segment from the second expander board is a serial data signal.

Abstract: A method for adjusting central processing unit (CPU) frequency according to the CPU utilization rate in a computer, the method includes the following steps. A Basic Input Output System (BIOS) is booted by turning on the computer. A performance monitor in the CPU is started by the BIOS. A timer is turned on by the BIOS. The system management interrupt program is read by the timer during a time period. A number of clock signals and time values is recorded by the performance monitor in two adjacent time periods. The CPU utilization rate is determined by the performance monitor according to number of clock signals, the time values, and a CPU clock speed. A CPU frequency is adjusted by the BIOS according to the CPU utilization rate. The computer's operation system (OS) is booted by the BIOS.

Abstract: A computer system including a first and second main boards, a judgment unit, a power supply, a first switch and second switch is provided. The judgment unit receives a first and second power start signals from the first and second main boards, and outputs a total power start signal. The power supply outputs a power reply signal according to the total power start signal. The first and second switches determine whether to output a power good signal individually according to the first and second power start signals. When one of the first and second power start signals is available, the total power start signal and the power reply signal are available, and the power supply outputs an operating voltage. When the first and second power start signals are unavailable, the total power start signal and the power reply signal are unavailable, and the power supply stops outputting the operating voltage.

Abstract: A computer system including a power supply and N main boards is provided, herein N is an integer greater than 1. The power supply generates a main power and a standby power. The N main boards respectively correspond to one standby voltage. The 1st to the (N?1)th main boards respectively generate the corresponding standby voltage by the main power in a power-on state, and respectively generate the corresponding standby voltage by the standby power in a power-off state. The Nth main board generates the corresponding standby voltage by the main power in the power-on and power-off state.

Abstract: A method for adjusting central processing unit (CPU) frequency according to the CPU utilization rate in a computer, the method includes the following steps. A Basic Input Output System (BIOS) is booted by turning on the computer. A performance monitor in the CPU is started by the BIOS. A timer is turned on by the BIOS. The system management interrupt program is read by the timer during a time period. A number of clock signals and time values is recorded by the performance monitor in two adjacent time periods. The CPU utilization rate is determined by the performance monitor according to number of clock signals, the time values, and a CPU clock speed. A CPU frequency is adjusted by the BIOS according to the CPU utilization rate. The computer's operation system (OS) is booted by the BIOS.

Abstract: A computer system including a power supply, a plurality of mainboards, and a power controller is provided. Each of the mainboards corresponds to a standby voltage, respectively. The power supply generates a standby power, and generates a main power according to a power enabling signal. The power controller is coupled between the power supply and the mainboards, for generating the power enabling signal and a control signal according to whether an amount of the mainboards is greater than a predetermined value, and selectively outputting the control signal to at least one of the mainboards. When the mainboards receive the control signal, regardless being in a booting state or a non-booting state, the mainboards receive the main power and converts the main power into a standby voltage corresponding thereto. When failing to receive the control signal, the mainboards convert the standby power into the standby voltage corresponding thereto.

Abstract: A sever including a chassis, at least one first tray, at least one second tray, a power supply module, multiple input/output interface circuit boards, and multiple mother boards is provided. The first and second trays are slidably disposed in the chassis, and the first and second trays can be drawn out of the chassis in opposite directions. The power supply module is disposed on a bottom plate of the chassis. The input/output interface circuit boards are disposed on the first tray, respectively. The power supply module is located between two input/output interface circuit boards. Each input/output interface circuit board has multiple input/output interfaces. The mother boards are disposed on the second trays, respectively. The input/output interface circuit boards and the power supply module are correspondingly electrically connected to the mother boards.

Abstract: An apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address is provided. The apparatus is composed by all cheap electronic devices, so as to achieve a purpose of lowering a cost for design. In addition, in the apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address of the invention, all the I2C slave devices are addressed by an I2C master device to perform the data transmission subsequently before a basic input/output system (BIOS) completes a power-on self-test (POST), but all the I2C slave devices are addressed by a system chip (for example, a baseboard management controller (BMC)) to perform the data transmission subsequently after the BIOS completes the POST. Therefore, the purpose of performing the data transmission for all the I2C slave devices on real time is achieved.

Abstract: A sever including a chassis, at least one first tray, at least one second tray, a power supply module, multiple input/output interface circuit boards, and multiple mother boards is provided. The first and second trays are slidably disposed in the chassis, and the first and second trays can be drawn out of the chassis in opposite directions. The power supply module is disposed on a bottom plate of the chassis. The input/output interface circuit boards are disposed on the first tray, respectively. The power supply module is located between two input/output interface circuit boards. Each input/output interface circuit board has multiple input/output interfaces. The mother boards are disposed on the second trays, respectively. The input/output interface circuit boards and the power supply module are correspondingly electrically connected to the mother boards.

Abstract: A computer system including a power supply, a plurality of mainboards, and a power controller is provided. Each of the mainboards corresponds to a standby voltage, respectively. The power supply generates a standby power, and generates a main power according to a power enabling signal. The power controller is coupled between the power supply and the mainboards, for generating the power enabling signal and a control signal according to whether an amount of the mainboards is greater than a predetermined value, and selectively outputting the control signal to at least one of the mainboards. When the mainboards receive the control signal, regardless being in a booting state or a non-booting state, the mainboards receive the main power and converts the main power into a standby voltage corresponding thereto. When failing to receive the control signal, the mainboards convert the standby power into the standby voltage corresponding thereto.

Abstract: A computer system including a chassis, a plurality of motherboards, a fan control module and a plurality of fans is provided. A plurality of motherboard position signal generating units is disposed in the chassis. Each of the motherboards includes a signal generating circuit and a board management controller. The signal generating circuit coordinates with one of the motherboard position signal generating units to generate a motherboard position signal. The board management controller receives the motherboard position signal and a motherboard working temperature signal to output a motherboard working state signal. The fan control module coupled to the board management controller of each of the motherboards receives the motherboard working state signals and generates a plurality of fan control signals accordingly. The fans coupled to the fan control module determine operation according the fan control signals.

Abstract: A computer system including a first and second main boards, a judgment unit, a power supply, a first switch and second switch is provided. The judgment unit receives a first and second power start signals from the first and second main boards, and outputs a total power start signal. The power supply outputs a power reply signal according to the total power start signal. The first and second switches determine whether to output a power good signal individually according to the first and second power start signals. When one of the first and second power start signals is available, the total power start signal and the power reply signal are available, and the power supply outputs an operating voltage. When the first and second power start signals are unavailable, the total power start signal and the power reply signal are unavailable, and the power supply stops outputting the operating voltage.

Abstract: A computer system including a power supply and N main boards is provided, herein N is an integer greater than 1. The power supply generates a main power and a standby power. The N main boards respectively correspond to one standby voltage. The 1st to the (N-1)th main boards respectively generate the corresponding standby voltage by the main power in a power-on state, and respectively generate the corresponding standby voltage by the standby power in a power-off state. The Nth main board generates the corresponding standby voltage by the main power in the power-on and power-off state.

Abstract: An apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address is provided. The apparatus is composed by all cheap electronic devices, so as to achieve a purpose of lowering a cost for design. In addition, in the apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address of the invention, all the I2C slave devices are addressed by an I2C master device to perform the data transmission subsequently before a basic input/output system (BIOS) completes a power-on self-test (POST), but all the I2C slave devices are addressed by a system chip (for example, a baseboard management controller (BMC)) to perform the data transmission subsequently after the BIOS completes the POST. Therefore, the purpose of performing the data transmission for all the I2C slave devices on real time is achieved.

Abstract: A power measuring apparatus including a voltage transformer, a voltage-current measuring circuit, and an operation unit is provided. The voltage transformer converts an input voltage signal into an output voltage signal. The voltage-current measuring circuit includes an inductor, a first resistor, a first capacitor and a second capacitor. A first end of the first inductor herein receives the output voltage signal and a second end thereof generates a voltage feedback signal. The operation unit performs an operation on the voltage feedback signal and a terminal current signal between the first terminal and the second terminal of the first capacitor so as to calculate a power signal. In this way, the accuracy of thermal test is effectively increased by the presented invention.