Patents by Inventor LIHONG XIAO

LIHONG XIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250064864
    Abstract: A microbial strain of Lachnospiraceae is a species of a genus of the family Lachnospiraceae (Lachnospiraceae sp.). The nucleotide sequence of 16S rRNA of the microbial strain of Lachnospiraceae is as shown in SEQ ID No. 1. The intestinal anaerobic microbial strain Lachnospiraceae sp. can inhibit the growth rate of tumors and can be used for preventing and/or treating tumors. The tumors include at least one of liver cancer, colon cancer, rectal cancer, colorectal cancer, lung cancer, breast cancer, cervical cancer, ovarian cancer, pancreatic cancer, cholangiocarcinoma, kidney cancer, and fibrosarcoma.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 27, 2025
    Inventors: GUOZHEN ZHAO, QIANWEN KUANG, CHEN XIAO, SHAOLI HUANG, ZHENZHEN LIU, PING KONG, LIHONG TAI, CHENCHEN ZHANG, YAJUN LIANG, RUIJUAN ZHU, YIBO XIAN, DONGYA ZHANG, XIANZHI JIANG
  • Patent number: 12077749
    Abstract: A strain of Bifidobacterium longum subsp. infantis Y46 with fimbriae (BI_Y46) includes a unique flagella structure, exhibits strong abilities in utilizing 2?-fucosyllactose (2?-FL), galacto-oligosaccharides and short-chain galacto-oligosaccharides, possesses excellent probiotic characteristics with higher levels of extracellular polysaccharides and surface proteins than a strain of Bifidobacterium longum subsp. infantis M63 (BI_M63) and a strain of Bifidobacterium longum subsp. infantis ATCC 15697 (BI_15697), and further displays stronger ability to tolerate gastric acid and inhibitory ability of the cell-free supernatant to Escherichia coli ATCC 15922 than the BI_15697. Therefore, the BI_Y46 has excellent probiotic potential and can be used to develop probiotics, infant food, prebiotic products, and functional foods.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: September 3, 2024
    Assignee: Northeast Agricultural University
    Inventors: Lili Zhang, Hui Sun, Zihe Xu, Ze Tan, Lihong Xiao, Mingxue He
  • Publication number: 20240182847
    Abstract: A strain of Bifidobacterium longum subsp. infantis Y46 with fimbriae (BI_Y46) includes a unique flagella structure, exhibits strong abilities in utilizing 2-fucosyllactose (2?-FL), galacto-oligosaccharides and short-chain galacto-oligosaccharides, possesses excellent probiotic characteristics with higher levels of extracellular polysaccharides and surface proteins than a strain of Bifidobacterium longum subsp. infantis M63 (BI_M63) and a strain of Bifidobacterium longum subsp. infantis ATCC 15697 (BI_15697), and further displays stronger ability to tolerate gastric acid and inhibitory ability of the cell-free supernatant to Escherichia coli ATCC 15922 than the BI_15697. Therefore, the BI_Y46 has excellent probiotic potential and can be used to develop probiotics, infant food, prebiotic products, and functional foods.
    Type: Application
    Filed: August 31, 2023
    Publication date: June 6, 2024
    Inventors: Lili ZHANG, Hui SUN, Zihe XU, Ze TAN, Lihong XIAO, Mingxue HE
  • Patent number: 10741390
    Abstract: A forming method of an epitaxial layer, a forming method of a 3D NAND memory and an annealing apparatus are provided. In the forming method of the epitaxial layer, a first annealing process is performed for eliminating a stress generated in a stacked structure. When performing the first annealing process, a silicon-containing mixture is formed on a sidewall and a bottom surface of a trench. Thus, after performing the first annealing process, a second annealing process is performed for removing the silicon-containing mixture disposed at the sidewall and the bottom surface of the trench, such that when subsequently forming the epitaxial layer, a growth interface of the epitaxial layer is a pure substrate material interface, so as to prevent from be formed a void defect in the epitaxial layer formed in the trench.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 11, 2020
    Assignee: Yangtz Memory Technologies Co., Ltd.
    Inventors: Haifeng Guo, Xiaojin Wang, Hongbin Zhu, Lin Lai, Teng Cheng, Lihong Xiao
  • Publication number: 20200161131
    Abstract: A forming method of an epitaxial layer, a forming method of a 3D NAND memory and an annealing apparatus are provided. In the forming method of the epitaxial layer, a first annealing process is performed for eliminating a stress generated in a stacked structure. When performing the first annealing process, a silicon-containing mixture is formed on a sidewall and a bottom surface of a trench. Thus, after performing the first annealing process, a second annealing process is performed for removing the silicon-containing mixture disposed at the sidewall and the bottom surface of the trench, such that when subsequently forming the epitaxial layer, a growth interface of the epitaxial layer is a pure substrate material interface, so as to prevent from be formed a void defect in the epitaxial layer formed in the trench.
    Type: Application
    Filed: March 13, 2019
    Publication date: May 21, 2020
    Inventors: Haifeng GUO, Xiaojin WANG, Hongbin ZHU, Lin LAI, Teng CHENG, Lihong XIAO
  • Patent number: 10347833
    Abstract: The present disclosure provides resistive random access memory and fabrication methods thereof. An exemplary fabrication method of the resistive random access memory includes providing a substrate; forming a bottom electrode on the substrate; forming a resistance switching layer on the bottom electrode; forming a barrier on the resistance switching layer; and forming a top electrode on the barrier layer. The barrier is used to prevent atoms in the top electrode from diffusing into the resistance switching layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Lihong Xiao
  • Patent number: 9741820
    Abstract: The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 22, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Lihong Xiao
  • Publication number: 20170092854
    Abstract: The present disclosure provides resistive random access memory and fabrication methods thereof. An exemplary fabrication method of the resistive random access memory includes providing a substrate; forming a bottom electrode on the substrate; forming a resistance switching layer on the bottom electrode; forming a barrier on the resistance switching layer; and forming a top electrode on the barrier layer. The barrier is used to prevent atoms in the top electrode from diffusing into the resistance switching layer.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 30, 2017
    Inventor: LIHONG Xiao
  • Publication number: 20160351686
    Abstract: The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 1, 2016
    Inventors: QIUHUA HAN, LIHONG XIAO