Patents by Inventor Lihu Rappoport

Lihu Rappoport has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10754655
    Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Adarsh Chauhan, Hong Wang, Jayesh Gaur, Zeev Sperber, Sumeet Bandishte, Lihu Rappoport, Stanislav Shwartsman, Kamil Garifullin, Sreenivas Subramoney, Adi Yoaz
  • Patent number: 10719355
    Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov, Lihu Rappoport, Stanislav Shwartsman, Hong Wang, Adi Yoaz, Ronak Singhal, Robert S. Chappell
  • Publication number: 20200192670
    Abstract: In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Saurabh Gupta, Niranjan Soundararajan, Ragavendra Natarajan, Jared Warner Stark, IV, Lihu Rappoport, Sreenivas Subramoney
  • Patent number: 10649783
    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.
    Type: Grant
    Filed: April 30, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Publication number: 20200133679
    Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
  • Patent number: 10579535
    Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Jared Warner Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
  • Publication number: 20200004542
    Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Adarsh Chauhan, Jayesh Gaur, Zeev Sperber, Sumeet Bandishte, Lihu Rappoport, Stanislav Shwartsman, Kamil Garifullin, Sreenivas Subramoney, Adi Yoaz, Hong Wang
  • Publication number: 20190370108
    Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Applicant: Intel Corporation
    Inventors: Zeev Sperber, Stanislav Shwartsman, Jared W. Stark, IV, Lihu Rappoport, Igor Yanover, George Leifman
  • Patent number: 10467011
    Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Zeev Sperber, Michael Mishaeli, Stanislav Shwartsman, Lev Makovsky, Adi Yoaz, Ofer Levy
  • Patent number: 10402263
    Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Stanislav Shwartsman, Jared W. Stark, IV, Lihu Rappoport, Igor Yanover, George Leifman
  • Publication number: 20190243684
    Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov, Lihu Rappoport, Stanislav Shwartsman, Hong Wang, Adi Yoaz, Ronak Singhal, Robert S. Chappell
  • Publication number: 20190213131
    Abstract: Systems and methods for stream cache memory retrieval include applying a stream cache to predict a sequence of instructions and data across multiple branches. Similar to a conventional computing cache, the stream cache stores and provides data or instructions more quickly than provided by slower data storage media, such as an instruction cache. The stream cache described herein provides the ability to predict instructions and data requests across multiple branches per cycle, and in particular across multiple taken branches per cycle. This stream cache increases instruction supply bandwidth while reducing overall power consumption by saving cycles of the branch predictor structures.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Ariel Sabba, Shani Rehana, Michael Tal, Suzan Baransi, Lihu Rappoport, Jared Warner Stark, Franck Sala
  • Publication number: 20190188142
    Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: Lihu RAPPOPORT, Jared Warner Stark iv, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
  • Publication number: 20190171515
    Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Zeev Sperber, Stanislav Shwartsman, Jared W. Stark, IV, Lihu Rappoport, Igor Yanover, George Leifman
  • Publication number: 20190012266
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 10095522
    Abstract: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Kamil Garifullin, Stanislav Shwartsman, Lihu Rappoport, Zeev Sperber, Pavel I. Kryukov, Andrey Kluchnikov, Igor Yanover, George Leifman, Alex Gerber, Jared W. Stark
  • Publication number: 20180165199
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 9690591
    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, processor logic delays the processing of a first instruction for a threshold amount of time if the first instruction within an instruction queue is fusible with a second instruction.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Patent number: 9678807
    Abstract: Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Lihu Rappoport
  • Patent number: 9552169
    Abstract: A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Jared W. Stark, Kamil Garifullin, Franck Sala, Pavel I. Kryukov, Stanislav Shwartsman