Abstract: A method for conditioning a ceramic layer with a thickness of less than 150 ?m over a substrate is provided. The ceramic layer is cleaned. A region of the ceramic layer is scanned with a pulsed excimer laser beam at a repetition rate of 3-300 Hz.

Abstract: A method for coating a part body for use in a plasma processing chamber is provided. The part body is received into a chamber. At least part of a surface of the part body is coated by physical vapor deposition or chemical vapor deposition with a coating with a thickness of no more than 30 microns consisting essentially of a Lanthanide series or Group III or Group IV element in an oxyfluoride.

Abstract: A method for conditioning a ceramic layer with a thickness of less than 150 ?m over a substrate is provided. The ceramic layer is cleaned. A region of the ceramic layer is scanned with a pulsed excimer laser beam at a repetition rate of 3-300 Hz.

Abstract: An apparatus for use in a plasma processing chamber is provided. The apparatus comprises part body and a coating with a thickness of no more than 30 microns consisting essentially of a Lanthanide series or Group III or Group IV element in an oxyfluoride covering a surface of the part body.

Abstract: A method for providing a protective layer over a substrate is provided. A ceramic layer is deposited over the substrate, wherein the ceramic layer has a porosity. A localized heating of a region of the ceramic layer to a temperature that causes the ceramic layer to melt without damaging the substrate is provided, wherein the melting the ceramic layer reduces the porosity or seals fissures or columnar grain boundaries. The region of the ceramic layer heated by the localized heating is scanned over the ceramic layer.

Abstract: A method of drilling holes comprises ductile mode drilling the holes in a component of a plasma processing apparatus with a cutting tool wherein the component is made of a nonmetallic hard and brittle material. The method comprises drilling each hole in the component by controlling a depth of cut while drilling such that a portion of the brittle material undergoes high pressure phase transformation and forms amorphous portions of the brittle material during chip formation. The amorphous portions of the brittle material are removed from each hole such that a wall of each hole formed in the component has an as drilled surface roughness (Ra) of about 0.2 to 0.8 ?m.

Abstract: A method of drilling holes comprises ductile mode drilling the holes in a component of a plasma processing apparatus with a cutting tool wherein the component is made of a nonmetallic hard and brittle material. The method comprises drilling each hole in the component by controlling a depth of cut while drilling such that a portion of the brittle material undergoes high pressure phase transformation and forms amorphous portions of the brittle material during chip formation. The amorphous portions of the brittle material are removed from each hole such that a wall of each hole formed in the component has an as drilled surface roughness (Ra) of about 0.2 to 0.8 ?m.

Abstract: A dual channel gas distributor can simultaneously distribute plasma species of an first process gas and a non-plasma second process gas into a process zone of a substrate processing chamber. The gas distributor has a localized plasma box with a first inlet to receive a first process gas, and opposing top and bottom plates that are capable of being electrically biased relative to one another to define a localized plasma zone in which a plasma of the first process gas can be formed. The top plate has a plurality of spaced apart gas spreading holes to spread the first process gas across the localized plasma zone, and the bottom plate has a plurality of first outlets to distribute plasma species of the plasma of the first process gas into the process zone. A plasma isolated gas feed has a second inlet to receive the second process gas and a plurality of second outlets to pass the second process gas into the process zone.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: Low K dielectric films exhibiting low mechanical stress may be formed utilizing various techniques in accordance with the present invention. In one embodiment, carbon-containing silicon oxide films are formed by plasma-assisted chemical vapor deposition at low temperatures (300° C. or less). In accordance with another embodiment, as-deposited carbon containing silicon oxide films incorporate a porogen whose subsequent liberation reduces film stress.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.