Abstract: The present disclosure discloses a method and device for data transmission between register files. The method includes that: data in a source register file are read at a Stage i of a pipeline; and the read data are transmitted to a destination register file using an idle instruction pipeline. With the method of the present disclosure, data and mask information are transmitted using an idle instruction pipeline, without addition of extra registers for data and control information buffering, thus reducing logic consumption as well as increasing utilization of an existing functional unit.

Abstract: The disclosure discloses a loopback structure and data loopback processing method of a processor. The loopback structure includes a register file unit, a data storing unit, and a data reading unit; wherein the register file unit is configured to provide a data reading-writing service for the data storing unit and the data reading unit; the data storing unit is connected to the register file unit, and is configured to read data via a reading port of the register file unit, to perform a data transformation on the read data, and to feed the transformed data back to the data reading unit; and the data reading unit is connected to the register file unit and the data storing unit, and is configured to transform the data fed back by the data storing unit, and to write the transformed data in the register file unit via a writing port of the register file unit. With the disclosure, it is possible to increase efficiency of the processor and decrease power consumption of the processor.

Abstract: The present disclosure discloses a method and device for data transmission between register files. The method includes that: data in a source register file are read at a Stage i of a pipeline; and the read data are transmitted to a destination register file using an idle instruction pipeline. With the method of the present disclosure, data and mask information are transmitted using an idle instruction pipeline, without addition of extra registers for data and control information buffering, thus reducing logic consumption as well as increasing utilization of an existing functional unit.

Abstract: The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management.