Patents by Inventor Liji Gopalakrishnan

Liji Gopalakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250218476
    Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.
    Type: Application
    Filed: January 7, 2025
    Publication date: July 3, 2025
    Inventors: John Eric LINSTADT, Liji Gopalakrishnan, Thomas Bogelsang
  • Patent number: 12347479
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: July 1, 2025
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Patent number: 12347480
    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: July 1, 2025
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, John Eric Linstadt, Liji Gopalakrishnan
  • Patent number: 12230355
    Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: February 18, 2025
    Assignee: Rambus Inc.
    Inventors: John Eric Linstadt, Liji Gopalakrishnan, Thomas Vogelsang
  • Publication number: 20250036581
    Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 30, 2025
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Publication number: 20240411640
    Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.
    Type: Application
    Filed: June 27, 2024
    Publication date: December 12, 2024
    Inventors: Frederick A. Ware, John E. Linstadt, Liji Gopalakrishnan
  • Publication number: 20240302977
    Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.
    Type: Application
    Filed: March 18, 2024
    Publication date: September 12, 2024
    Inventors: Thomas Vogelsang, Liji Gopalakrishnan
  • Patent number: 12072817
    Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: August 27, 2024
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Publication number: 20240282357
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Application
    Filed: March 7, 2024
    Publication date: August 22, 2024
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Patent number: 12050513
    Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: July 30, 2024
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John E. Linstadt, Liji Gopalakrishnan
  • Publication number: 20240176497
    Abstract: ABSTRACT OF DISCLOSURE A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 30, 2024
    Inventors: Liji GOPALAKRISHNAN, Thomas VOGELSANG, John Eric LINSTADT
  • Publication number: 20240152470
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 9, 2024
    Inventors: Liji Gopalakrishnan, Frederick A. Ware, Brent S. Haukness
  • Patent number: 11972121
    Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 30, 2024
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Liji Gopalakrishnan
  • Publication number: 20240127882
    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
    Type: Application
    Filed: October 30, 2023
    Publication date: April 18, 2024
    Inventors: Thomas VOGELSANG, John Eric Linstadt, Liji Gopalakrishnan
  • Patent number: 11955161
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 9, 2024
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Patent number: 11921650
    Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Rambus Inc.
    Inventor: Liji Gopalakrishnan
  • Patent number: 11868619
    Abstract: A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 9, 2024
    Assignee: Rambus Inc.
    Inventors: Liji Gopalakrishnan, Thomas Vogelsang, John Eric Linstadt
  • Publication number: 20230418770
    Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.
    Type: Application
    Filed: June 29, 2023
    Publication date: December 28, 2023
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Patent number: 11842761
    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, John Eric Linstadt, Liji Gopalakrishnan
  • Patent number: 11829308
    Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: November 28, 2023
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar