Patents by Inventor Lijiang L. Wang

Lijiang L. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Yield optimization for design library elements at library element level or at product level
    Patent number: 8799836
    Abstract: In one embodiment, at least one design library element having a design marker shape is applied to a yield checking tool having library element types, each having a yield checking deck threshold and a marker shape. The design marker shape is compared to each of the marker shapes. A determination is made as to whether the design library element satisfies the yield checking deck threshold associated with the library element type having a matching marker shape. In another embodiment, a product design formed from a design library elements each having a design marker shape is applied to the yield checking tool in a similar manner. In instances where the design library elements do not satisfy the yield checking deck threshold, then the design library element is updated by modifying the design library elements, placement of the design library elements in the product design, and/or wiring connecting the design library elements.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeanne P. S. Bickford, Anand Kumaraswamy, Terry M. Lowe, Mark S. Styduhar, Lijiang L. Wang
  • Identifying parasitic diode(s) in an integrated circuit physical design
    Patent number: 8756554
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN
    Publication number: 20130067425
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Application
    Filed: May 15, 2012
    Publication date: March 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Identifying parasitic diode(s) in an integrated circuit physical design
    Patent number: 8191030
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN
    Publication number: 20090150842
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 11, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Identifying parasitic diode(s) in an integrated circuit physical design
    Patent number: 7490303
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: February 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Method and system for improving integrated circuit manufacturing productivity
    Patent number: 7076749
    Abstract: A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Daniel N. Maynard, Gustavo E. Tellez, Lijiang L. Wang, Peter S. Wissell