Abstract: A self-destructive type safe medical needle comprises: a sleeve with an inner cavity, a needle base which can do reciprocating motion in the inner cavity and a needle head, a lock catch head buckled with the needle base, a lock catch head buckled with the needle base, and a conduit connected with the inside of the lock catch head, wherein the sleeve is provided with a barrier block and a lock catch block in the inner cavity, and the needle base is provided with a limiting part which is propped against and matched with the barrier block and a deformable locking part which is locked and matched with the lock catch block. The needle avoids cross infection between patients, secondary use of needle and puncture of staff after use or in the process of destroying. Further, this needle also can realize self-destruction and prevent man-made rotation of the medical needle.

Abstract: A method for making an interferometric taper waveguide (I-TWG) with high critical dimension uniformity and small line edge roughness for a heat assisted magnetic recording (HAMR) head, wherein the method includes creating an I-TWG film stack with two hard mask layers on top of an I-TWG core layer sandwiched between two cladding layers, defining a photoresist pattern over the I-TWG film stack using deep ultraviolet lithography, transferring the pattern to the first hard mask layer using reactive ion etching (RIE), forming a temporary I-TWG pattern on the second hard mask layer using RIE, transferring the temporary pattern to the I-TWG core using RIE, refilling the cladding layer, and planarizing using chemical mechanical planarization (CMP).

Abstract: A mode converter for use in a Heat-assisted magnetic recording (HAMR) read head to couple or bend light (e.g., from an external laser diode) into a tapered waveguide, and subsequently, to a near field transducer is provided. The mode converter may have an ultra-sharp tip, e.g., less than 200 nm to achieve a desired optical output. Manufacturing such a mode converter involves a two-pattern transform process, where overlay control (using a first edge, such as a right edge, as a reference layer relative to which positioning of a second edge, such as a left edge, is measured) allows for aligning of the right and left edges of a tip portion of the mode converter to ultimately create the ultra-sharp tip.

Abstract: Embodiments of the present invention provide an access processing method, an apparatus, and a system, where the method includes: generating, by a capability enabling gateway, a RAT selection policy according to context information of a UE, and sending a RAT selection request that includes the RAT selection policy to an inter-RAT coordination controller corresponding to a cell in which the UE is located, so that the inter-RAT coordination controller determines an access standard of the UE according to the RAT selection policy. In this way, network utilization is improved, and service quality can be ensured and improved for an end user.

Abstract: A method for making an interferometric taper waveguide (I-TWG) with high critical dimension uniformity and small line edge roughness for a heat assisted magnetic recording (HAMR) head, wherein the method includes creating an I-TWG film stack with two hard mask layers on top of an I-TWG core layer sandwiched between two cladding layers, defining a photoresist pattern over the I-TWG film stack using deep ultraviolet lithography, transferring the pattern to the first hard mask layer using reactive ion etching (RIE), forming a temporary I-TWG pattern on the second hard mask layer using RIE, transferring the temporary pattern to the I-TWG core using RIE, refilling the cladding layer, and planarizing using chemical mechanical planarization (CMP).

Abstract: A method for making an interferometric taper waveguide (I-TWG) with high critical dimension uniformity and small line edge roughness for a heat assisted magnetic recording (HAMR) head, wherein the method includes creating an I-TWG film stack with two hard mask layers on top of an I-TWG core layer sandwiched between two cladding layers, defining a photoresist pattern over the I-TWG film stack using deep ultraviolet lithography, transferring the pattern to the first hard mask layer using reactive ion etching (RIE), forming a temporary I-TWG pattern on the second hard mask layer using RIE, transferring the temporary pattern to the I-TWG core using RIE, refilling the cladding layer, and planarizing using chemical mechanical planarization (CMP).

Abstract: Embodiments of the present invention relate to reducing the size variation on a wafer fabrication. In some embodiments, at least a portion the backfill material over features larger than a threshold size is etched or milled to provide backfill protrusions over those features. The backfill protrusions are configured to reduce the size variation across the fabrication. Embodiments of the invention may be used in fabrication of many types of devices, such as tapered wave guides (TWG), near-field transducers (NFT), MEMS devices, EAMR optical devices, optical structures, bio-optical devices, micro-fluidic devices, and magnetic writers.

Abstract: Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

Abstract: A method of removing photoresist beneath an overlayer includes estimating a rapid temperature change for a photoresist layer to produce cracking in the overlayer. The temperature chance is estimated so that the cracking of the overlayer is sufficient to allow a liftoff solution to penetrate below the overlayer during a liftoff step. The method further includes baking the photoresist layer and chilling the photoresist layer after baking to produce the rapid temperature change. The method then includes lifting off the photoresist layer using the liftoff solution.

Abstract: A shaper mask for particle flux includes a central portion extending from a body of the shaper mask along a first axis to block at least a first portion of a particle flux through the shaper mask from a first direction. The mask also includes at least one off-axis portion. Each off-axis portions extends from the body of the shaper mask along a respective second axis different from the first axis. Each off-axis portion is shaped to block a respective second portion of the particle flux traveling through the shaper mask from a second direction different from the first direction.

Abstract: Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

Abstract: A method of lifting off photoresist beneath an overlayer includes providing a structure including photoresist and depositing an overlayer impenetrable to a liftoff solution over the photoresist and a field region around the structure. The method also includes forming a mask over the structure and ion milling to remove the overlayer in the field region not covered by the mask. The method then includes lifting off the photoresist using the liftoff solution.

Abstract: A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Abstract: A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Abstract: A method and apparatus for converting an analog input voltage signal to a discrete signal, the method including generating at least one reference voltage and at least one secondary voltage. The method further including selecting at least one voltage between the at least one reference voltage and the at least one secondary voltage and generating at least one intermediate voltage based on the at least one voltage and at least one digital code. The at least one intermediate voltage and the analog input voltage further being used to generate at least one comparison signal and the discrete signal being generated based on the at least one comparison signal and the at least one digital code.