Abstract: The present disclosure provides a method and apparatus for coupling a superconducting qubit. The method includes: determining a target coupling strength between a target read cavity and a qubit, a first target frequency of the qubit, and a second target frequency of the target read cavity; initializing a read coupling port configuration layout based on a configuration of the qubit, a relative position of the qubit to the target read cavity; calculating a to-be-measured coupling strength between the qubit and the read coupling port, based on the read coupling port configuration layout, the first target frequency, and the second target frequency; and in response to detecting that the to-be-measured coupling strength and the target coupling strength satisfy a preset condition, generating, based on the second target frequency and the read coupling port configuration layout, a complete layout comprising the qubit and the target read cavity.

Abstract: Provided is a simulation method, electronic device, and storage medium relating to the field quantum computers and quantum simulation. The simulation method can include obtaining a first normal mode frequency of a first target device with adjustable frequency among at least two devices of a quantum chip layout through simulation; determining resonance-related information of the first target device and a second target device in a resonant state among the at least two devices; where the second target device is a device with adjustable or non-adjustable frequency among the at least two devices; and obtaining a target coupling strength between the first and second target devices based on the first normal mode frequency of the first target device and the resonance-related information.

Abstract: Provided is a coupling component applied to a quantum chip, a quantum chip and a quantum computing device. The coupling component includes a first electrode plate and a second electrode plate. The first electrode plate includes a first coupling port and a second coupling port. The second electrode plate includes a third coupling port and a fourth coupling port. At least one of the following conditions is satisfied: a first coupling strength formed by coupling the first coupling port with a first qubit is different from a second coupling strength formed by coupling the second coupling port with a second qubit, and a third coupling strength formed by coupling the third coupling port with the first qubit is different from a fourth coupling strength formed by coupling the fourth coupling port with the second qubit.

Abstract: Provided is a simulation method, an electronic device and a storage medium, relating to the field of computer and in particular to the field of quantum computer and quantum simulation. The simulation method can includes obtaining first frequency information of a first target device among at least two devices of a quantum chip layout through simulation, and obtaining second frequency information of a second target device among the at least two devices through simulation; and obtaining a coupling strength between the first target device and the second target device among the at least two devices based on the first frequency information and the second frequency information.

Abstract: A method is provided that includes: determining a frequency range of a reading device, and corresponding quality factors of reading cavities and filters; determining frequency ranges of the reading cavities and filters based on the frequency range of the reading device; determining a frequency of each reading cavity and filter based on the frequency ranges of the reading cavity and filter and the corresponding quality factors; determining a length of each reading cavity and a length of each filter respectively, such that a difference value between its frequency and a determined frequency does not exceed a first threshold; determining a spacing and a coupling length between the reading cavities and the filters to make it close to a preset quality factor; and performing simulation verification on a layout of a superconducting quantum chip based on the lengths, spacing and coupling length of the reading cavities and the filters.

Abstract: Provided are a quantum chip structure, a determining method, a device and a storage medium, and relates to the field of computer technology, and in particular, to the field of quantum computation. The quantum chip structure includes: a ring structure composed of n center qubits, where two adjacent center qubits in the ring structure are connected through a coupler; and n is a natural number greater than or equal to 3; and two-linear structures drawn from a center qubit Qi toward outside of the ring structure; where a first linear structure in the two-linear structures contains ai first qubits; and a second linear structure in the two-linear structures contains bi second qubits. In this way, a quantum chip structure with high connectivity is obtained.

Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which are related to a field of quantum computing. The specific implementation includes: a superconducting circuit structure, including: at least three computational qubits; a bus qubit connected to the respective computational qubits, wherein couplings between two of the computational qubits connected by the bus qubit are equivalent; and coupler qubits disposed between the respective computational qubits and the bus qubit, to connect the respective computational qubits to the bus qubits, wherein the coupler qubit is configured to regulate coupling strength between the computational qubit and the bus qubit. Couplings between any two computational qubits may be realized, so that an operation of a quantum gate between any two computational qubits is achieved, while crosstalk between computational qubits may be effectively suppressed.

Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which relate to the field of quantum computing. The superconducting circuit structure includes: at least two qubits; a connector, coupled with the two qubits respectively, to realize transversal coupling with each of the two qubits; and a coupler, coupled with the two qubits respectively, to realize longitudinal coupling with each of the two qubits. Therefore, the ?z?z parasitic coupling between the qubits is effectively removed, and a two-qubit gate with high fidelity is obtained.

Abstract: The present disclosure discloses a high-fidelity superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer, which relate to the field of quantum computation. The specific implementation is as follows: computation qubits; a coupling device configured to be coupled with two computation qubits, respectively; a connecting component disposed between a computation qubit and the coupling device to couple the computation qubit with the coupling device, so as to implement a target quantum gate based on the coupling device and the computation qubit.

Abstract: A method is provided.

Abstract: The present disclosure provides a quantum circuit processing method and a quantum circuit processing device on a quantum chip, and an electronic device, and it relates to the field of quantum computing technology, in particular to the field of quantum circuit technology. The method includes: obtaining a first swap fidelity for measuring connectivity of the quantum chip, the first swap fidelity being determined in accordance with first information, the first information being used to represent a topological structure of the quantum chip, the topological structure indicating that the quantum chip includes at least two physical quantum bits, the first swap fidelity being used to represent an average state maintenance level of logic quantum bits obtained through analog exchanging quantum states of any two of the physical quantum bits; and performing quantum circuit processing on the quantum chip in accordance with the first swap fidelity.

Abstract: A quantum chip is provided, includes: a first substrate and a second substrate arranged opposite to each other, wherein a plurality of qubits and a plurality of first controllers are arranged on a surface of the first substrate facing the second substrate, each of the plurality of qubits is coupled with at least one of the plurality of first controllers, and a plurality of control signal transmission parts are arranged on a surface of the second substrate facing the first substrate; and a plurality of connecting pieces, connected between the first substrate and the second substrate, and configured to connect the plurality of first controllers to the plurality of control signal transmission parts in a one-to-one corresponding mode.

Abstract: A method is provided. The method includes determining a corresponding relationship between a pulse enveloping parameter and a single pulse duration, and determining a parameter to be optimized; and determining a maximum pulse number, an initialized current pulse number and a preset error tolerance. The method further includes executing an iterative operation including determining a quantum gate matrix to be implemented and a value of a loss function based on the current pulse number and the parameter to be optimized; adjusting a group of parameter values of the parameter to be optimized to minimize the value of the loss function; determining an error with a target quantum gate matrix after the value of the loss function is minimized; and in response to that the current pulse number is less than the maximum pulse number and the error is greater than the error tolerance, adding one to the current pulse number.

Abstract: A method for routing wires on a chain quantum chip is provided. The method may include: encoding, according to a corresponding relationship between multiple pins of a chain quantum chip and inlets of multiple qubits on a qubit chain, the multiple pins and multiple inlets respectively, where the multiple pins include multiple first pins parallel to an extending direction of the qubit chain; determining and connecting a first inlet with a first target pin, where a distance between an abscissa of the first inlet and an abscissa of the first target pin satisfies a first preset condition; and connecting, according to codes of remaining inlets and codes of remaining pins, the remaining inlets with the remaining pins in a one-to-one correspondence.

Abstract: A digital signature method, a signature information verification method, a related apparatus and an electronic device are provided. The digital signature method includes: obtaining a to-be-sent file and a private key used by a first electronic device for digital signature, the private key including a first invertible matrix; generating L second tensors based on the first invertible matrix and a first tensor, the L second tensors including the first tensor and a tensor isomorphic to the first tensor; digitally signing the to-be-sent file based on a second invertible matrix and the first tensor, to obtain a first character string; constructing a hash value of a root node of a hash tree based on the L second tensors; generating signature information of the to-be-sent file based on the first character string, the first invertible matrix, the second invertible matrix, the L second tensors and the hash value of the root node.

Abstract: A control pulse generation method, a system, a device and a storage medium are provided, which are related to the field of quantum computing. The method includes: acquiring a system Hamiltonian; acquiring an initial control pulse of a quantum logic gate included in a parameterized quantum circuit to obtain an initial pulse sequence for a gate sequence formed for all the quantum logic gates in the parameterized quantum circuit, which is obtained through simulation based on the system Hamiltonian; acquiring system state information of the quantum system obtained after applying the initial pulse sequence to the target quantum hardware device; adjusting a parameter of the parameterized quantum circuit based on a relationship between the system state information and target state information needed to be achieved by the target quantum control task, to adjust a pulse parameter of the initial pulse sequence to obtain a target pulse sequence.

Abstract: A simulation method in quantum control is provided, which is related to a field of quantum control. The specific implementation scheme includes: acquiring a hardware parameter corresponding to a quantum system and a target quantum gate required to be realized by the quantum system; acquiring a pulse function represented on the basis of discrete time slices; determining target step sizes corresponding to the discrete time slices in the pulse function, to obtain pulse parameter values within time durations corresponding to the target step sizes corresponding to the time slices and the pulse function; and obtaining simulation quantum gates within the time durations corresponding to the target step sizes on the basis of obtained pulse parameter values within the time durations corresponding to the target step sizes and the hardware parameter of the quantum system, until obtaining a target simulation quantum gate within a preset pulse time duration.

Abstract: A quantum control pulse generation method, a device, and a storage medium are provided, which are related to the field of quantum computation. The method includes: constructing, based on relevant physical parameters of a target quantum hardware structure, a system Hamiltonian of a quantum system characterized by the target quantum hardware structure; obtaining an initial control pulse set matching the target quantum hardware structure; obtaining, based on the system Hamiltonian, system state information of the quantum system by simulation; and optimizing the initial control pulse in the initial control pulse set based on at least a relationship between the system state information of the quantum system and target state information that needs to be achieved by the target quantum task, to obtain a target control pulse sequence by simulation.

Abstract: This application discloses a digital signature method, a signature information verification method, a related apparatus and an electronic device, and relates to the field of information security in quantum computing. The digital signature method includes: acquiring a to-be-sent file and a private key used by a first electronic device for digital signature, where the private key includes a first invertible matrix; generating, based on a randomly generated second invertible matrix and a first tensor, a second tensor isomorphic to the first tensor; using a hash function to digitally sign the to-be-sent file based on the second tensor, to obtain a first character string; generating, based on the first character string, the first invertible matrix and the second invertible matrix, signature information provided by the first electronic device for the to-be-sent file.

Abstract: The present disclosure provides superconducting circuit architecture, a superconducting quantum chip, and a superconducting quantum computer including a plurality of coupling devices. The superconducting circuit architecture includes: a first qubit and a second qubit, and a first coupling device and a second coupling device. The first coupling device is coupled to the first qubit and the second qubit through a first connector, and the second coupling device is coupled to the first qubit and the second qubit through a second connector. The frequencies of the first qubit and the second qubit are between a frequency of the first coupling device and a frequency of the second coupling device, and a nonlinear strength of the first coupling device and a nonlinear strength of the second coupling device are opposite in sign.