Patents by Inventor Lijuan Zou

Lijuan Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210520
    Abstract: A semiconductor device includes a row of source/drain regions delineating a frontside and a backside opposite the frontside of the semiconductor device. A front gate cut from the frontside of the device has a depth that is less than a height of a gate structure for the semiconductor device. A back gate cut from the backside of the semiconductor device contacts the front gate cut.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250203988
    Abstract: Semiconductor devices include an active part that includes a semiconductor channel and a gate stack. A frontside part includes a frontside electrical contact to the active part. A backside part includes a backside electrical contact to the active part. A lower gate cap electrically insulates the gate from the backside electrical contact and includes a first region of the lower gate cap that is in contact with a shallow trench isolation (STI) structure of the backside part and a second region of the lower gate cap that is in contact with a surface of the backside electrical contact.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250194156
    Abstract: A semiconductor device includes a first nanosheet stack on a front side of a semiconductor substrate, a second nanosheet stack on the front side of the semiconductor substrate separated from the first nanosheet stack by a source/drain region, and a deep nanosheet trench extends into the source/drain region between first and second nanosheet stacks. A source/drain is in the deep nanosheet trench and includes a bottom end having a backside source/drain divot formed therein. A deep trench liner is interposed between the deep nanosheet trench and the source/drain, the deep trench liner having an opening exposing the bottom end of the source/drain. A backside contact is on a backside of the semiconductor device, the backside contact physically contacting the exposed bottom end of the source/drain.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 12, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Eric Miller
  • Publication number: 20250185298
    Abstract: A microelectronic structure that includes a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor. The lower nanosheet transistor includes a lower source/drain and the upper nanosheet transistor includes an upper source/drain. An airgap located between the upper source/drain and the lower source/drain. The airgap is vertically aligned with the upper source/drain and the lower source/drain. A first layer located between the airgap and the lower source/drain.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 5, 2025
    Inventors: Lijuan Zou, Jay William Strane, Junli Wang, Brent A. Anderson, Ruilong Xie, Albert M. Chu
  • Publication number: 20250185299
    Abstract: A microelectronic structure including a first nanosheet transistor that includes a first source/drain and a second nanosheet transistor that includes a second source/drain. The first source/drain and the second source/drain are aligned along a common axis. The common axis is parallel to a gate direction. A backside width of the first source/drain and a backside width of the second source/drain are different as measured along the common axis. A bottom dielectric isolation layer located on a backside surface of the second source/drain. A backside contact located on a backside surface of the first source/drain.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 5, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250169172
    Abstract: A semiconductor device includes a dielectric isolation bar disposed in a region between an n-type active region and a p-type active region. The dielectric isolation bar has a first tapered portion disposed within a contact where the contact connects to the n-type active region or the p-type active region and a second tapered portion that cuts through portions of a buried power rail layer, wherein the dielectric isolation bar electrically isolates a lateral portion of the contact from surrounding structures and separates portions of the buried power rail layer.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 22, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Chih-Chao Yang
  • Publication number: 20250151400
    Abstract: A semiconductor structure includes a transistor device at a first side of the semiconductor structure, a control circuit at the first side of the semiconductor structure, and a resistor-capacitor circuit including a resistor and a capacitor. The resistor is in a power delivery network at a second side of the semiconductor structure and the capacitor is at the first side of the semiconductor structure. A first electrode of the capacitor is coupled to a first power rail in the power delivery network at the second side of the semiconductor structure. A second electrode of the capacitor is coupled to a second power rail in the power delivery network at the second side of the semiconductor structure. An input of the control circuit is coupled to the resistor. A gate of the transistor device is coupled to an output of the control circuit.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250113560
    Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Lijuan Zou, Jay William Strane, Junli Wang, Brent A. Anderson, Ruilong Xie, Albert M. Chu
  • Publication number: 20250085724
    Abstract: Disclosed is a test device and method for remote control parking, falling within the technical field of testing. The method provided by the present disclosure includes the following steps: responding to a remote control parking instruction sent by a portable terminal, and acquiring position and pose data of a vehicle in real-time; injecting function loss conditions; determining a stopping position of the vehicle according to the position and pose data if an alarm signal or a parking success signal sent by an in-vehicle infotainment system is received; and determining a test result of remote control parking according to the stopping position of the vehicle and the function loss conditions. The present disclosure is used to test the response of a vehicle parking under the function loss condition.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Inventors: Shasha TANG, Xiaodi TIAN, Fujian HE, Guokai JIANG, Bowei ZOU, Feiyan WU, Xuebin SHAO, Rupeng DOU, Yu WANG, Xiucheng LI, Jiaxu FENG, Zhiqiang YANG, Quan WEN, Wenjun SUN, Xiaolong ZHAO, Jinna FAN, Lijuan ZOU
  • Publication number: 20250079309
    Abstract: A semiconductor device fabrication method is provided and includes executing front-end-of-line (FEOL) processing to form first and second source/drain (S/D) epitaxy, forming a middle-of-line (MOL) contact to the first S/D epitaxy, executing a self-aligned backside S/D cut to form an opening in which respective sides of each of the first and second S/D epitaxy are exposed, depositing metallic material along the respective sides of each of the first and second S/D epitaxy in the opening and forming silicide from the metallic material whereby the silicide at the first S/D epitaxy contacts the MOL contact and the sides of the first S/D epitaxy.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Chanro Park
  • Publication number: 20250063817
    Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes an active device region and a passive device region, the active device region and the passive device region being separated by a single diffusion break, where the passive device region includes a first passive device. The first passive device includes a first diffusion region and a second diffusion region, the first and the second diffusion region being vertically connected by a lightly doped region, where the first diffusion region is connected to a backside power distribution network through a first direct backside contact (BSCA) and the second diffusion region is connected to a back-end-of-line (BEOL) structure through a first middle-of-line contact. A method of forming the same is also provided.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Anthony I. Chou
  • Publication number: 20250048715
    Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for providing power vias through a wafer backside. In a non-limiting embodiment of the invention, a gate and a source or drain (S/D) region are formed on a substrate. A bi-layer liner is formed in a gate cut of the gate. The bi-layer liner includes a first liner on sidewalls of the gate cut and a second liner between the first liner. A top portion of the second liner is replaced with a first portion of a backside power via and the semiconductor device is flipped. A bottom portion of the second liner is replaced with a second portion of the backside power via.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Lijuan Zou, Tao Li, FENG LIU, Ruilong Xie
  • Patent number: 12191388
    Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: January 7, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Mignot, Su Chen Fan, Jing Guo, Lijuan Zou
  • Publication number: 20240420990
    Abstract: A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. Each field effect transistor includes source/drain regions located on opposite sides of the field effect transistors. A shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. The shallow trench isolation region has a tapered profile. A backside isolation region is embedded within the shallow trench isolation region and cuts through the source/drain regions. The backside isolation region has a reverse tapered profile.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Lijuan Zou, Tao Li, Ruilong Xie, Chanro Park
  • Publication number: 20240421037
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A plurality of nanosheet recesses are formed within a substrate. A placeholder structure is formed on a bottom surface within each nanosheet recess. A first source/drain region is formed within a first nanosheet recess. A second source/drain region is formed within the second nanosheet recess. The semiconductor structure is flipped. The substrate is removed respective to a sidewall spacer of the placeholder structure and a first etch stop layer of the placeholder structure. Backside interlayer dielectric is formed. A backside contact trench to the second source drain region is formed by removing a portion of the backside interlayer dielectric over the second source/drain region and removing exposed portions of the first etch stop layer, the sidewall spacer, and a silicon buffer layer of the placeholder structure. A backside contact is formed within the trench.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 19, 2024
    Inventors: Lijuan Zou, Shahrukh Khan, Biswanath Senapati, Ruilong Xie
  • Publication number: 20230145135
    Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 11, 2023
    Inventors: Yann Mignot, Su Chen Fan, Jing Guo, Lijuan Zou
  • Patent number: 11489044
    Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Yi Song, Lijuan Zou
  • Patent number: 11158786
    Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Chih-Chao Yang, Lijuan Zou, John Arnold
  • Patent number: 11015256
    Abstract: Methods of forming near field transducers (NFTs) including electrodepositing a plasmonic material.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventors: Lien Lee, Jie Gong, Venkatram Venkatasamy, Yongjun Zhao, Lijuan Zou, Dongsung Hong, Ibro Tabakovic, Mark Ostrowski
  • Publication number: 20210151558
    Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Zhenxing Bi, Kangguo Cheng, Yi Song, Lijuan Zou