Patents by Inventor Lijun SHAN

Lijun SHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040152
    Abstract: A memory cell group and a manufacturing method therefor are provided. The memory cell group includes: a first resistive memory cell and a second resistive memory cell. The first resistive memory cell includes a first electrode, a first resistive layer and a second electrode, the first electrode is connected to a first line through a first metal layer, the second electrode is connected to a second line, and the first line and the second line together achieve independent control over the first resistive memory cell. The second resistive memory cell includes the second electrode, a second resistive layer and a third electrode, the third electrode is connected to a third line through a second metal layer, and the third line and the second line together achieve independent control over the second resistive memory cell. The first and second resistive memory cells share the second electrode.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 30, 2025
    Applicant: XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Taiwei CHIU, Lijun SHAN, Tingying SHEN
  • Publication number: 20240349629
    Abstract: A semiconductor integrated circuit device includes a resistive layer having a trench-like structure with an upward opening, a first electrode located on an outer side of the resistive layer, and a second electrode located on an inner side of the resistive layer; the first electrode and the second electrode are opposite to each other on two sides of a sidewall of the resistive layer; and the resistive layer, the first electrode and the second electrode form a first memory cell. A manufacturing method includes forming a first electrode on a substrate, the substrate including a first via connected with a first metal layer; etching a recess in the first electrode at a position staggered from the first via and forming a resistive layer in the recess; and forming a second electrode in the opening of the resistive layer to obtain a first memory cell.
    Type: Application
    Filed: August 18, 2022
    Publication date: October 17, 2024
    Applicant: XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Yajun ZHANG, Tingying SHEN, Lijun SHAN, Taiwei CHIU, Yu LIU, Szu-chun KANG
  • Publication number: 20240251686
    Abstract: Disclosed in embodiments of the present application are a linear resistive element and a preparation method therefor. The linear resistive element includes a substrate unit, a function unit and an electrode unit. The substrate unit includes a substrate layer, which is configured to connect the function unit and the electrode unit. The electrode unit includes a first electrode and a second electrode. The first and second electrodes are deposited on the substrate layer, and the function unit is connected between the first and second electrodes. The function unit includes first dielectric layers and resistive layers. The first dielectric layers and the resistive layers are deposited on the substrate layer in an alternately stacked manner. A number of the resistive layers is at least two, and a conductive filament for conductively connecting the first and second electrodes is formed in each of the resistive layers.
    Type: Application
    Filed: January 30, 2024
    Publication date: July 25, 2024
    Applicant: XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: SZU-CHUN KANG, Tingying SHEN, Lijun SHAN, Taiwei CHIU, Yu LIU, Yajun ZHANG
  • Publication number: 20230320238
    Abstract: The present disclosure provides a semiconductor integrated circuit device and a manufacturing method therefor. In the device, an electrode in a resistive random-access memory (RRAM) cell is directly connected to a metal layer, thereby omitting the steps of filling a connection via with other metal materials (such as tungsten) and of polishing. The manufacturing process is hence simplified, and different degrees of depressions caused by polishing are correspondingly reduced. The uniformity of resistive performance of the RRAM and the quality of the semiconductor integrated circuit device are hence greatly improved. In addition, a resistive layer having a trench structure is formed by using a trench where an original connection via is located, thereby embedding the entire RRAM cell into the trench. The structure of the RRAM cell is more compact, a gap between RRAM cells is smaller, and the requirements for miniaturization and high density can thus be better met.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Taiwei CHIU, Lijun SHAN, Tingying SHEN
  • Publication number: 20230144512
    Abstract: The present disclosure discloses a method for manufacturing a resistive switching element, including: performing an etching process, a deposition process and a polishing process alternately to prepare the bottom electrode, the resistive switching layer and the top electrode; and optimizing at least one of the bottom electrode, the resistive switching materials and the oxygen storage layer by using the sidewall process when preparing the bottom electrode and the resistive switching materials, so as to reduce a contact area between the bottom electrode and the resistive switching materials, and/or reduce a contact area between the resistive switching materials and the oxygen storage layer. The method could form conductive filaments in the resistive switching layer, and a low resistive state and high resistive state are realized by forming and breaking conductive filaments.
    Type: Application
    Filed: November 6, 2022
    Publication date: May 11, 2023
    Inventors: Yu LIU, Tingying SHEN, SZU-CHUN KANG, Taiwei CHIU, Danyun WANG, Lijun SHAN