Abstract: A voice recognition device, a voice control system and a voice communication system are disclosed, wherein the voice recognition device includes: a loudspeaker. The loudspeaker includes: a vibration unit, configured to receive an acoustic signal; a conversion unit, configured to convert the acoustic signal into an electric signal; and a processor, connected with the conversion unit and configured to receive the electric signal and recognize the electric signal. The disclosure solves the technical problem that a voice control product contains many devices, and is structured complicatedly.

Abstract: A method and system for processing information based on dual-tone multifrequency, and a receiving terminal are disclosed in the present document. The method includes: a sending terminal establishing a voice call with a receiving terminal; the sending terminal receiving input key information, encoding the key information into dual-tone multifrequency information, and transmitting the dual-tone multifrequency information and voice call audio information to the receiving terminal together; and the receiving terminal decoding and restoring the dual-tone multifrequency information to the key information; determining a type of the key information according to a preset key information judgment policy, and performing corresponding operations according to the key information.

Abstract: A method and system for processing information based on dual-tone multifrequency, and a receiving terminal are disclosed in the present document. The method includes: a sending terminal establishing a voice call with a receiving terminal; the sending terminal receiving input key information, encoding the key information into dual-tone multifrequency information, and transmitting the dual-tone multifrequency information and voice call audio information to the receiving terminal together; and the receiving terminal decoding and restoring the dual-tone multifrequency information to the key information; determining a type of the key information according to a preset key information judgment policy, and performing corresponding operations according to the key information.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address (es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address (es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.