Patents by Inventor Lik Huay Lim
Lik Huay Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10823759Abstract: A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.Type: GrantFiled: November 5, 2018Date of Patent: November 3, 2020Assignee: XILINX, INC.Inventors: Lik Huay Lim, Andy Widjaja, King Yon Lew, Mohsen H. Mardi, Xuejing Che
-
Patent number: 10783308Abstract: A graphical tool for a design of a substrate of an integrated circuit device is described. The graphical tool comprises a processor configured to: display locations of probes for a first plurality of contact elements associated with the substrate; display locations of BGA contact elements associated with the substrate; identify interconnect elements between the first plurality of contact elements and the BGA contact elements; and display connections lines representing the identified interconnect elements. A method of designing a substrate of an integrated circuit device is also described.Type: GrantFiled: December 20, 2018Date of Patent: September 22, 2020Assignee: XILINIX, INC.Inventors: Lik Huay Lim, Andy Widjaja, King Yon Lew, Xuejing Che, Mohsen H. Mardi
-
Publication number: 20200141976Abstract: A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.Type: ApplicationFiled: November 5, 2018Publication date: May 7, 2020Applicant: Xilinx, Inc.Inventors: Lik Huay Lim, Andy Widjaja, King Yon Lew, Mohsen H. Mardi, Xuejing Che
-
Patent number: 10613137Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.Type: GrantFiled: December 1, 2017Date of Patent: April 7, 2020Assignee: XILINX, INC.Inventors: Mohsen H. Mardi, Lik Huay Lim, King Yon Lew, Andy Widjaja
-
Patent number: 10571517Abstract: Examples of the present disclosure generally relate to a probe head assembly having modular interposer and a test system having the same. In one example, a probe head assembly includes a rigid stiffener plate, a PIB substrate, a bracket, a plurality of interposers disposed in the bracket, a probe card board electrically coupled by a plurality of contact pins disposed through the interposers to the PIB substrate, and a probe card electrically coupled to the probe card board. The PIB substrate, the interposers and the probe card board are sandwiched between the stiffener plate and the probe card.Type: GrantFiled: December 1, 2017Date of Patent: February 25, 2020Assignee: XILINX, INC.Inventors: Mohsen H. Mardi, Lik Huay Lim, King Yon Lew, Andy Widjaja
-
Publication number: 20190170816Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Applicant: Xilinx, Inc.Inventors: Mohsen H. Mardi, Lik Huay Lim, King Yon Lew, Andy Widjaja
-
Patent number: 8170823Abstract: A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.Type: GrantFiled: February 8, 2011Date of Patent: May 1, 2012Assignee: Altera CorporationInventors: Daniel Tun Lai Chow, San Wong, Vincent K. Tsui, Lik Huay Lim, Man On Wong
-
Patent number: 7890279Abstract: A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.Type: GrantFiled: August 11, 2008Date of Patent: February 15, 2011Assignee: Altera CorporationInventors: Daniel Tun Lai Chow, San Wong, Vincent K. Tsui, Lik Huay Lim, Man On Wong