Patents by Inventor Lilach CHOONA

Lilach CHOONA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12561793
    Abstract: There is provided a system and method of examination of semiconductor specimens. The method includes generating a sequence of anomaly scores corresponding to a sequence of specimens sequentially fabricated and examined during a fabrication process, comprising, for each given specimen: obtaining an image of the given specimen acquired by an examination tool; using a machine learning (ML) model to process the image and obtaining an anomaly map indicative of pattern variation in the image; and deriving, based on the anomaly map, an anomaly score indicative of level of pattern variation presented in the given specimen, wherein the anomaly score is correlated with a defectivity score related to defect detection in a correlation relationship, and has higher detection sensitivity than the defectivity score; and analyzing the sequence of anomaly scores to monitor on-going process stability, thereby providing defect related prediction along the fabrication process based on the correlation relationship.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: February 24, 2026
    Assignee: Applied Materials Israel Ltd.
    Inventors: Noam Tal, Boris Levant, Sergey Sinitsa, Boaz Sturlesi, Shay Yogev, Assaf Ariel, Lilach Choona, Shaul Pres
  • Patent number: 12469124
    Abstract: There is provided a system and method of examination of a semiconductor specimen. The method includes obtaining an e-beam image representative of a given layer of a given structure on the specimen in runtime, processing at least the e-beam image using a ML model, and obtaining yield related prediction with respect to the given structure prior to performing an electrical test. The ML model is previously trained using a training set comprising multiple stacks of e-beam images corresponding to multiple sites of the given structure on one or more training specimens, each stack of e-beam images representative of the at least given layer of a respective site; and test data acquired from an electrical test performed at the multiple sites and related to actual yield of the training specimens, the test data respectively correlated with the stacks of e-beam images and used as ground truth thereof.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: November 11, 2025
    Assignee: Applied Materials Israel Ltd.
    Inventors: Boris Levant, Noam Tal, Ran Yacoby, Lilach Choona, Shaul Pres, Jasmin Sonia Linshiz, Shay Yogev, Assaf Ariel
  • Publication number: 20240281956
    Abstract: There is provided a system and method of examination of semiconductor specimens. The method includes generating a sequence of anomaly scores corresponding to a sequence of specimens sequentially fabricated and examined during a fabrication process, comprising, for each given specimen: obtaining an image of the given specimen acquired by an examination tool; using a machine learning (ML) model to process the image and obtaining an anomaly map indicative of pattern variation in the image; and deriving, based on the anomaly map, an anomaly score indicative of level of pattern variation presented in the given specimen, wherein the anomaly score is correlated with a defectivity score related to defect detection in a correlation relationship, and has higher detection sensitivity than the defectivity score; and analyzing the sequence of anomaly scores to monitor on-going process stability, thereby providing defect related prediction along the fabrication process based on the correlation relationship.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Noam TAL, Boris LEVANT, Sergey SINITSA, Boaz STURLESI, Shay YOGEV, Assaf ARIEL, Lilach CHOONA, Shaul PRES
  • Publication number: 20240281958
    Abstract: There is provided a system and method of examination of a semiconductor specimen. The method includes obtaining an e-beam image representative of a given layer of a given structure on the specimen in runtime, processing at least the e-beam image using a ML model, and obtaining yield related prediction with respect to the given structure prior to performing an electrical test. The ML model is previously trained using a training set comprising multiple stacks of e-beam images corresponding to multiple sites of the given structure on one or more training specimens, each stack of e-beam images representative of the at least given layer of a respective site; and test data acquired from an electrical test performed at the multiple sites and related to actual yield of the training specimens, the test data respectively correlated with the stacks of e-beam images and used as ground truth thereof.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Boris LEVANT, Noam TAL, Ran YACOBY, Lilach CHOONA, Shaul PRES, Jasmin Sonia LINSHIZ, Shay YOGEV, Assaf ARIEL