Patents by Inventor Lilia May
Lilia May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111090Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Robert A. May, Tarek Ibrahim, Shriya Seshadri, Kristof Darmawikarta, Hiroki Tanaka, Changhua Liu, Bai Nie, Lilia May, Srinivas Pietambaram, Zhichao Zhang, Duye Ye, Yosuke Kanaoka, Robin McRee
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Publication number: 20230223278Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Shuckman
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Patent number: 11631595Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.Type: GrantFiled: November 8, 2021Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
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Publication number: 20220183157Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: INTEL CORPORATIONInventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
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Patent number: 11272619Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.Type: GrantFiled: September 2, 2016Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
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Publication number: 20220059367Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
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Patent number: 11195727Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.Type: GrantFiled: June 15, 2020Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
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Publication number: 20210307172Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.Type: ApplicationFiled: September 2, 2016Publication date: September 30, 2021Applicant: INTEL CORPORATIONInventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
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Patent number: 11107780Abstract: An integrated-circuit package substrate includes a pseudo-stripline that is shielded below a lower solder-resist layer and an upper solder-resist layer, where an upper shielding plane is sandwiched between the lower and upper solder-resist layers. The lower solder-resist layer can at least partially overlap a landing-pad region of a landing-pad via that penetrates a top build-up layer which is contacted by the lower solder-resist layer.Type: GrantFiled: June 7, 2019Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Lilia May, Robert Alan May, Amruthavalli Pallavi Alur, Robert L. Sankman
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Patent number: 11075130Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.Type: GrantFiled: March 30, 2017Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Lisa Ying Ying Chen, Lauren Ashley Link, Robert Alan May, Amruthavalli Pallavi Alur, Kristof Kuwawi Darmawikarta, Siddharth K. Alur, Sri Ranga Sai Boyapati, Andrew James Brown, Lilia May
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Publication number: 20200388582Abstract: An integrated-circuit package substrate includes a pseudo-stripline that is shielded below a lower solder-resist layer and an upper solder-resist layer, where an upper shielding plane is sandwiched between the lower and upper solder-resist layers. The lower solder-resist layer can at least partially overlap a landing-pad region of a landing-pad via that penetrates a top build-up layer which is contacted by the lower solder-resist layer.Type: ApplicationFiled: June 7, 2019Publication date: December 10, 2020Inventors: Lilia May, Robert Alan May, Amruthavalli Pallavi Alur, Robert L. Sankman
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Publication number: 20200312675Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Amanda
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Patent number: 10685850Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.Type: GrantFiled: June 30, 2016Date of Patent: June 16, 2020Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
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Publication number: 20200176355Abstract: A semiconductor device package structure is provided, which includes a substrate, one or more dies coupled to the substrate, and a heat pipe device. In an example, the heat pipe device may include a conduit that is at least partially embedded within the substrate. The heat pipe device may have a first region coupled to the one or more dies. In an example, the conduit may include a first path for flow of vapor from the first region to an opposing second region. The conduit may further include a second path for flow of liquid from the second region to the first region.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Applicant: Intel CorporationInventors: Robert A. May, Kristof Darmawikarta, Rahul Jain, Lilia May, Maroun Moussallem, Prithwish Chatterjee
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Patent number: 10573622Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.Type: GrantFiled: September 29, 2017Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Lilia May, Edward R. Prack
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Publication number: 20190393109Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.Type: ApplicationFiled: March 30, 2017Publication date: December 26, 2019Inventors: Lisa Ying Ying CHEN, Lauren Ashley LINK, Robert Alan MAY, Amruthavalli Pallavi ALUR, Kristof Kuwawi DARMAWIKARTA, Siddharth K. ALUR, Sri Ranga Sai BOYAPATI, Andrew James BROWN, Lilia MAY
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Publication number: 20190103377Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Lilia May, Edward R. Prack
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Patent number: 10049971Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: GrantFiled: April 3, 2017Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
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Publication number: 20170207152Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
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Patent number: 9613933Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: GrantFiled: March 5, 2014Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin