Patents by Inventor Lilian Kamal, legal representative

Lilian Kamal, legal representative has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8232177
    Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wagdi Abadeer, Lilian Kamal, legal representative, Kiran V Chatty, Robert J Gauthier, Jr., Jed H Rankin, Robert R Robison, William Tonti
  • Patent number: 8110483
    Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Jr., Robert R. Robison, William R. Tonti
  • Patent number: 8021950
    Abstract: Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, John J. Ellis-Monaghan, Jeffrey P. Gambino, Tom C. Lee