Abstract: A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

Abstract: A method for detecting static-current failure devices in a chip is provided. The method includes providing a chip and determining existence of a static-current failure device in the chip. The method also includes detecting positions of a plurality of hotspots in the chip when the existence of the static-current failure devices is determined; and selecting a common circuit path according to position information of the hotspots in a circuit layout file of the chip. Further, the method includes converting a circuit layout of the common circuit path into a corresponding electrical diagram and marking the positions of the plurality of hotspots on corresponding positions on the electrical diagram; and detecting a shared device of the hotspots in the electrical diagram. Further, the method includes marking a position of the shared device in the circuit layout as a position of a static-current failure device.

Abstract: A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

Abstract: A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

Abstract: A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

Abstract: A method for detecting static-current failure devices in a chip is provided. The method includes providing a chip and determining existence of a static-current failure device in the chip. The method also includes detecting positions of a plurality of hotspots in the chip when the existence of the static-current failure devices is determined; and selecting a common circuit path according to position information of the hotspots in a circuit layout file of the chip. Further, the method includes converting a circuit layout of the common circuit path into a corresponding electrical diagram and marking the positions of the plurality of hotspots on corresponding positions on the electrical diagram; and detecting a shared device of the hotspots in the electrical diagram. Further, the method includes marking a position of the shared device in the circuit layout as a position of a static-current failure device.