Patents by Inventor Lily Jiang
Lily Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200378815Abstract: A system for determining the level of solids accumulated in a sand separator has a vibratory level sensor and a solid separator control system. The vibratory level sensor includes a vibratory rod and an exciter connected to the vibratory rod. In some embodiments, a vibration sensor is connected to the vibratory rod to monitor changes in the vibration of the rod. In other embodiments, changes in vibration are measured by looking at the rotational speed and power inputs at the exciter.Type: ApplicationFiled: May 30, 2020Publication date: December 3, 2020Applicant: Baker Hughes Oilfield Operations LLCInventors: Lily Jiang, Jason Angolano, Sam Stroder, Gregory Adams
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Patent number: 10698427Abstract: Embodiments of the present disclosure include a method including receiving first impact data. The method includes receiving second impact data. The method includes applying a first filter to both the first impact data and the second impact data. The method includes applying a second filter to both the first impact data and the second impact data. Filtering includes time and frequency based discriminating filter to isolate specific signatures that representatively indicate impact signatures generated by the sand on the interrogator. The method includes comparing the first impact data and the second impact data for corresponding signatures. The method includes identifying a corresponding signature in both the first impact data and the second impact data. The method includes determining the corresponding signature meets a threshold criterion. The method includes determining one or more particulate properties based at least in part on the corresponding peak.Type: GrantFiled: August 22, 2018Date of Patent: June 30, 2020Assignee: GE OIL & GAS PRESSURE CONTROL LPInventors: Vimal V. Shah, Lily Jiang, Lembit Salasoo
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Publication number: 20190308136Abstract: An in-line pipe contactor includes a first tubular having an outer surface and an inner surface. The inner surface defines a first flow path and the outer surface defines, in part, a second flow path. A second tubular is arranged radially outwardly of the first tubular. The second tubular includes an outer surface portion and an inner surface portion. The inner surface portion defines at least in part, the second flow path. A first end cap is mounted at the first end. The first end cap supports a first plurality of atomizers. At least one of the first plurality of atomizers is directed along the first flow path. A second end cap is mounted at the second end portion. The second end cap supports a second plurality of atomizers. At least one of the second plurality of atomizers is directed along the second flow path.Type: ApplicationFiled: April 5, 2019Publication date: October 10, 2019Applicant: Baker Hughes, a GE company, LLCInventors: Sunder Ramachandran, James Ott, Mahendra Ladharam Joshi, Pejman Kazempoor, Grant Lynn Hartman, Lily Jiang, Matthew L. George
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Publication number: 20190308133Abstract: A method of removing impurities from formation fluids includes introducing a formation fluid into a first end of a first tubular, directing the formation fluid along a first flow path toward a second end of the first tubular, redirecting the formation fluid along a second flow path defined by a second tubular arranged radially outwardly of the first flow path toward the first end, spraying a treatment fluid along the first flow path into the formation fluid, and directing a treated formation fluid through an outlet fluidically connected to the second flow path.Type: ApplicationFiled: April 5, 2019Publication date: October 10, 2019Applicant: Baker Hughes, a GE company, LLCInventors: Sunder Ramachandran, James Ott, Mahendra Ladharam Joshi, Pejman Kazempoor, Grant Lynn Hartman, Lily Jiang, Matthew L. George
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Patent number: 9252010Abstract: A method used for processing a structure in manufacturing of a semiconductor device may include polishing the structure to form a polished structure. The polished structure may include a metal member, a dielectric layer that contacts the metal member, and a particle that contacts at least one of the metal member and the dielectric layer. The method may further include applying an organic acid to the polished structure to remove at least a portion of the particle. The particle may be substantially removed, such that satisfactory quality of the semiconductor may be provided.Type: GrantFiled: February 13, 2014Date of Patent: February 2, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Lily Jiang, Cindy Li
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Publication number: 20150132954Abstract: A method used for processing a structure in manufacturing of a semiconductor device may include polishing the structure to form a polished structure. The polished structure may include a metal member, a dielectric layer that contacts the metal member, and a particle that contacts at least one of the metal member and the dielectric layer. The method may further include applying an organic acid to the polished structure to remove at least a portion of the particle. The particle may be substantially removed, such that satisfactory quality of the semiconductor may be provided.Type: ApplicationFiled: February 13, 2014Publication date: May 14, 2015Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily JIANG, Cindy LI
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Patent number: 8889510Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.Type: GrantFiled: July 12, 2013Date of Patent: November 18, 2014Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: De Yuan Xiao, Lily Jiang, Gary Chen, Roger Lee
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Patent number: 8679923Abstract: A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.Type: GrantFiled: November 27, 2012Date of Patent: March 25, 2014Assignee: Semiconductor Manufacturing International Corp.Inventors: Junzhu Cao, Lily Jiang, Cindy Li, Creek Zhu
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Publication number: 20130302951Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.Type: ApplicationFiled: July 12, 2013Publication date: November 14, 2013Inventors: De Yuan Xiao, Lily Jiang, Gary Chen, Roger Lee
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Patent number: 8513727Abstract: Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.Type: GrantFiled: September 28, 2010Date of Patent: August 20, 2013Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Deyuan Xiao, Lily Jiang, Gary Chen, Roger Lee
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Publication number: 20130157449Abstract: A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.Type: ApplicationFiled: November 27, 2012Publication date: June 20, 2013Inventors: JUNZHU CAO, LILY JIANG, CINDY LI, CREEK ZHU
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Patent number: 8105897Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: GrantFiled: December 24, 2009Date of Patent: January 31, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jiang Guang Chang
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Patent number: 8105898Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: GrantFiled: December 24, 2009Date of Patent: January 31, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jian Guang Chang
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Patent number: 8105899Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region.Type: GrantFiled: December 24, 2009Date of Patent: January 31, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jian Guang Chang
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Patent number: 8097508Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: GrantFiled: December 24, 2009Date of Patent: January 17, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jian Guang Chang
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Publication number: 20110163369Abstract: Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.Type: ApplicationFiled: September 28, 2010Publication date: July 7, 2011Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Deyuan Xiao, Lily Jiang, Gary Chen, Roger Lee
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Publication number: 20100248468Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: ApplicationFiled: December 24, 2009Publication date: September 30, 2010Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Cai, Jiang Guang Chang
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Publication number: 20100227464Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: ApplicationFiled: December 24, 2009Publication date: September 9, 2010Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: LILY JIANG, MENG FENG CAI, JIAN GUANG CHANG
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Publication number: 20100227465Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region.Type: ApplicationFiled: December 24, 2009Publication date: September 9, 2010Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: LILY JIANG, MENG FEN CAI, JIAN GUANG CHANG
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Publication number: 20100190329Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: ApplicationFiled: December 24, 2009Publication date: July 29, 2010Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: LILY JIANG, MENG FENG CAI, JAIN GUANG CHANG