Patents by Inventor Lily Khor
Lily Khor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11114367Abstract: A package is disclosed. The package includes a leadframe, and a first die, attached to the leadframe. The package also includes first bond wires, each attached to one of the first bond pads of the first die and to one of the leads of the leadframe, and a package body molded over each of a portion of the die pad of the leadframe, a portion of the leads of the leadframe, a first portion of the first die, and one or more of the first bond wires. The molded package body defines a cavity, and a second portion of the first die contacts neither of the die pad and the package body. The package also includes a second die having second bond pads, where the second die is attached to the first die. The package also includes second bond wires, each attached to the first and second die.Type: GrantFiled: September 10, 2019Date of Patent: September 7, 2021Assignee: Carsem (M) SDN. BHD.Inventors: Lily Khor, Phuah Kian Keung
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Publication number: 20200219800Abstract: A package is disclosed. The package includes a leadframe, and a first die, attached to the leadframe. The package also includes first bond wires, each attached to one of the first bond pads of the first die and to one of the leads of the leadframe, and a package body molded over each of a portion of the die pad of the leadframe, a portion of the leads of the leadframe, a first portion of the first die, and one or more of the first bond wires. The molded package body defines a cavity, and a second portion of the first die contacts neither of the die pad and the package body. The package also includes a second die having second bond pads, where the second die is attached to the first die. The package also includes second bond wires, each attached to the first and second die.Type: ApplicationFiled: September 10, 2019Publication date: July 9, 2020Applicant: Carsem (M) SDN. BHD.Inventors: Lily Khor, Phuah Kian Keung
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Patent number: 10468319Abstract: An electronic package is formed by placing a semiconductor die within an opening in a leadframe and performing a first molding operation. The die is wirebonded to the leadframe and a final encapsulation is performed with a second molding operation.Type: GrantFiled: April 20, 2017Date of Patent: November 5, 2019Assignee: CARSEM (M) SDN. BHD.Inventors: Yan Shan Ng, Lily Khor
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Publication number: 20180211902Abstract: A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Applicant: Carsem (M) SDN. BHD.Inventors: Lily Khor, Lynn Simporios Guirit
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Publication number: 20180150673Abstract: An electronic package is formed by placing a semiconductor die within an opening in a leadframe and performing a first molding operation. The die is wirebonded to the leadframe and a final encapsulation is performed with a second molding operation.Type: ApplicationFiled: April 20, 2017Publication date: May 31, 2018Inventors: Yan Shan Ng, Lily Khor
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Patent number: 9935039Abstract: A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.Type: GrantFiled: November 10, 2014Date of Patent: April 3, 2018Assignee: Carsem (M) SDN. BHD.Inventors: Lily Khor, Lynn Simporios Guirit
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Patent number: 9640517Abstract: A stacked electronic package includes a substrate and conductive straps each having sides, a top, and a bottom opposite the top. Each conductive strap is coupled along the bottom to an upper surface of the substrate and is separate from others of the conductive straps. A length of at least one of the sides is greater than a width of at least another one of the sides. An encapsulant extends over the upper surface and side surfaces of the substrate and the sides of the conductive straps. A passive electronic component is disposed over the conductive straps, and each conductive strap is coupled along the top to a terminal of the passive electronic component.Type: GrantFiled: October 29, 2014Date of Patent: May 2, 2017Assignee: CARSEM (M) SDN. BHD.Inventors: Thong Kai Choh, Lily Khor, Oo Choo Yee
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Publication number: 20150237721Abstract: A stacked electronic package includes a substrate and conductive straps each having sides, a top, and a bottom opposite the top. Each conductive strap is coupled along the bottom to an upper surface of the substrate and is separate from others of the conductive straps. A length of at least one of the sides is greater than a width of at least another one of the sides. An encapsulant extends over the upper surface and side surfaces of the substrate and the sides of the conductive straps. A passive electronic component is disposed over the conductive straps, and each conductive strap is coupled along the top to a terminal of the passive electronic component.Type: ApplicationFiled: October 29, 2014Publication date: August 20, 2015Inventors: Thong Kai Choh, Lily Khor, Oo Choo Yee
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Publication number: 20150179553Abstract: A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.Type: ApplicationFiled: November 10, 2014Publication date: June 25, 2015Inventors: Lily Khor, Lynn Simporios Guirit
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Patent number: 9048397Abstract: A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED.Type: GrantFiled: January 6, 2014Date of Patent: June 2, 2015Assignee: Carsem (M) SDN. BHD.Inventors: Edmund Sales Cabatbat, Lily Khor, Ho Tuck Ming
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Publication number: 20150087087Abstract: A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED.Type: ApplicationFiled: January 6, 2014Publication date: March 26, 2015Applicant: CARSEM (M) SDN. BHD.Inventors: Edmund Sales Cabatbat, Lily Khor, Ho Tuck Ming
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Publication number: 20120043655Abstract: A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.Type: ApplicationFiled: November 1, 2011Publication date: February 23, 2012Applicant: Carsem (M) Sdn. Bhd.Inventors: Lily Khor, Yong Lam Wai, Lau Choong Keong
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Patent number: 8071470Abstract: A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.Type: GrantFiled: May 29, 2009Date of Patent: December 6, 2011Assignee: Carsem (M) SDN. BHD.Inventors: Lily Khor, Yong Lam Wai, Lau Choong Keong
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Publication number: 20100102444Abstract: A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.Type: ApplicationFiled: May 29, 2009Publication date: April 29, 2010Applicant: Carsem (M) Sdn. Bhd.Inventors: Lily Khor, Yong Lam Wai, Lau Choon Keong
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Patent number: 7273767Abstract: A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface, prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of an integrated circuit die formed on the wafer without covering the plurality of bonding pads, curing the curable material and dicing the semiconductor wafer to separate the integrated circuit die from other integrated circuit die formed upon the wafer.Type: GrantFiled: May 4, 2005Date of Patent: September 25, 2007Assignee: Carsem (M) Sdn. Bhd.Inventors: King Hoo Ong, Lily Khor, Boon Pek Liew, Kai Choh Thong
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Publication number: 20060148127Abstract: A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface, prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of an integrated circuit die formed on the wafer without covering the plurality of bonding pads, curing the curable material and dicing the semiconductor wafer to separate the integrated circuit die from other integrated circuit die formed upon the wafer.Type: ApplicationFiled: May 4, 2005Publication date: July 6, 2006Applicant: Carsem Semiconductor Sdn. Bhd.Inventors: King Ong, Lily Khor, Boon Liew, Kai Thong
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Patent number: 6953711Abstract: There is disclosed a flip-chip-type method of assembling semiconductor devices. A one-step encapsulation process promotes adhesion of the die to the lead fingers and prevents the potential of shorts developing between the adjacent bumps or lead fingers. Conventional mold compound is used to reduce localized stress caused by coefficient of thermal expansion (CTE) mismatch between the die and substrate, or the lead frame.Type: GrantFiled: August 11, 2003Date of Patent: October 11, 2005Assignee: Carsem (M) Sdn. Bhd.Inventors: Lily Khor, Au Keng Yeun
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Publication number: 20050037545Abstract: There is disclosed a flip-chip-type method of assembling semiconductor devices. A one-step encapsulation process promotes adhesion of the die to the lead fingers and prevents the potential of shorts developing between the adjacent bumps or lead fingers. Conventional mold compound is used to reduce localized stress caused by coefficient of thermal expansion (CTE) mismatch between the die and substrate, or the lead frame.Type: ApplicationFiled: August 11, 2003Publication date: February 17, 2005Inventors: Lily Khor, Au Yeun
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Patent number: 6482680Abstract: There is disclosed a flip-chip-type method of assembling semiconductor devices. The proposed invention offer one step encapsulation process to promote adhesion of die to the lead finger and prevent the potential of shorts from developing between the adjacent bumps (13) or lead fingers. Conventional mold compound (15) is used to reduce localized stress causes by coefficient of thermal expansion (CTE) mismatch between the die (11) and substrate, or the lead frame (12). This is particularly favorable in promoting greater mechanical robustness of the semiconductor devices. With one step encapsulation process proposed by the present invention, manufacturing process is made simpler, faster and relatively cheaper.Type: GrantFiled: July 20, 2001Date of Patent: November 19, 2002Assignee: Carsem Semiconductor SDN, BHD.Inventors: Lily Khor, Ong King Hoo