Abstract: A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.

Abstract: A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.

Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

Abstract: A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another node without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.

Abstract: A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol distributed (SPPD). A snoop filter in the SPS tracks which nodes may be using various memory addresses. A scalability port protocol central (SPPC) is responsible for processing messages to support coherent and non-coherent transactions in the system.

Abstract: In a multi-node computing system, the originating receiving device receives a broadcast request, decodes the broadcast request, and transmits a broadcast header to a primary tagging device. The primary tagging device generates at least one tagged broadcast header and transmits the at least one tagged broadcast header to the originating receiving device. The originating receiving device transmits tagged broadcast transaction(s) to broadcast receiving device(s). The broadcast receiving device(s) transmits the tagged broadcast transaction(s) to a broadcast node(s). The broadcast node(s) transmits a node completion signal(s) to the broadcast receiving device(s). The broadcast receiving device(s) transmits all of the node completion signal(s) to the primary tagging device. The primary tagging device transmits a transaction completion signal to the originating receiving device.

Abstract: A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.

Abstract: According to one embodiment, a method is disclosed. The method includes receiving a first request from a first node in a multi-node computer system to invalidate a first cache line at a second node. The method also includes receiving a second request from the second node to invalidate the first cache line at the first node and detecting the concurrent requests at conflict detection circuitry.

Abstract: According to one embodiment, a method is disclosed. The method comprises receiving a read request from a first node in a multi-node computer system to read data from a memory at a second node. Subsequently, a write request from a third node is received to write data to the memory at the second node. The read request and write request is detected at conflict detection circuitry. Finally, read data from the memory at the second node is transmitted to the first node.

Abstract: A method and apparatus are described for supporting the full MESI (Modified, Exclusive, Shared or Invalid) protocol in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that a responding node other than the requesting node and the home node for the desired data has a copy of the data in an ambiguous state. The switch resolves this ambiguous state by snooping the remote node. After resolving the ambiguous state, the read request transaction is completed.

Abstract: A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.

Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

Abstract: According to one embodiment, a method is disclosed. The method includes receiving a first request from a first node in a multi-node computer system to invalidate a first cache line at a second node. The method also includes receiving a second request from the second node to invalidate the first cache line at the first node and detecting the concurrent requests at conflict detection circuitry.

Abstract: According to one embodiment, a method is disclosed. The method comprises receiving a read request from a first node in a multi-node computer system to read data from a memory at a second node. Subsequently, a write request from a third node is received to write data to the memory at the second node. The read request and write request is detected at conflict detection circuitry. Finally, read data from the memory at the second node is transmitted to the first node.

Abstract: An interrupt delivery system is provided for delivering interrupt requests in a multi-node computer system. The interrupt delivery system includes a pair of scaleable node controllers, each of which supports at least one microprocessor. The scaleable node controllers are coupled to a scalability port switch, which receives an interrupt request. The scalability port switch determines an address of one of the scaleable node controllers from the interrupt request. Based on the address, the scalability port switch then transmits the interrupt request to the correct scaleable node controller.

Abstract: In a multi-node system, a method and apparatus to implement a locked-bus transaction is described. In one embodiment, a bus agent initiates a locked-bus transaction and a node controller defers the transaction so that it will be initiated again at a later time. The node controller then sends the locked bus request to one or more other node controllers in the system, which prevent bus transaction at their respective busses. Once the requesting node controller receives confirmation that the other nodes are locked, it can allow the locked-bus transaction to proceed from the bus agent.

Abstract: In a multi-node system, a method and apparatus to implement a request such as a purge TLB entry request is described. In one embodiment, a processor initiates a purge TLB request and any other processors assert a signal in response (pending completion of the request). A node controller coupled to the processor via a bus asserts the same signal to indicate that the request has not been completed. The node controller can then send the request to other node controller (potentially via a switching agent), so that other processors in the multi-node system can complete the request. Once all processors in the other nodes have completed the request, the node controller can deassert the signal, which indicates to the requesting processor that the request has been completed at all processor outside of its node.

Abstract: A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

Abstract: A method of invalidating cache a line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another nodes without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.