Patents by Inventor Lily Pao Looi
Lily Pao Looi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10241952Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.Type: GrantFiled: September 29, 2015Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
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Patent number: 9952644Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 31, 2015Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Mahesh Wagh, Lily Pao Looi
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Patent number: 9952643Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 31, 2015Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Mahesh Wagh, Lily Pao Looi
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Publication number: 20160116959Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 31, 2015Publication date: April 28, 2016Applicant: Intel CorporationInventors: Mahesh Wagh, Lily Pao Looi
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Publication number: 20160110309Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 31, 2015Publication date: April 21, 2016Applicant: Intel CorporationInventors: Mahesh Wagh, Lily Pao Looi
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Publication number: 20160085711Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.Type: ApplicationFiled: September 29, 2015Publication date: March 24, 2016Applicant: Intel CorporationInventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
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Patent number: 9146610Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.Type: GrantFiled: March 4, 2011Date of Patent: September 29, 2015Assignee: Intel CorporationInventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
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Patent number: 9110666Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.Type: GrantFiled: March 4, 2011Date of Patent: August 18, 2015Assignee: Intel CorporationInventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
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Patent number: 8850250Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.Type: GrantFiled: June 1, 2010Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: Lily Pao Looi, Stephan J. Jourdan, Selim Bilgin, Sin S. Tan, Anant S. Deval, Srikanth T. Srinivasan
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Publication number: 20140281639Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Mahesh Wagh, Lily Pao Looi
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Patent number: 8782456Abstract: Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.Type: GrantFiled: December 24, 2010Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Sin S. Tan, Srikanth T. Srinivasan, Sivakumar Radhakrishnan, Stephan J. Jourdan, Lily Pao Looi
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Publication number: 20120079159Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.Type: ApplicationFiled: March 4, 2011Publication date: March 29, 2012Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
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Publication number: 20110296222Abstract: Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.Type: ApplicationFiled: December 24, 2010Publication date: December 1, 2011Inventors: Sin S. Tan, Srikanth T. Srinivasan, Sivakumar Radhakrishnan, Stephan J. Jourdan, Lily Pao Looi
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Publication number: 20110296216Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Inventors: Lily Pao Looi, Stephan J. Jourdan, Selim Bilgin, Sin S. Tan, Anant S. Deval, Srikanth T. Srinivasan
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Patent number: 7376775Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.Type: GrantFiled: December 29, 2003Date of Patent: May 20, 2008Assignee: Intel CorporationInventors: Lily Pao Looi, Stanley Steven Kulick, Dean A Mulla, Ashish Gupta, Keith R. Pflederer, Shivnandan D. Kaushik, Mohan J. Kumar, James B. Crossland
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Patent number: 7093079Abstract: Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.Type: GrantFiled: December 17, 2002Date of Patent: August 15, 2006Assignee: Intel CorporationInventors: Tuan M. Quach, Lily Pao Looi, Kai Cheng
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Patent number: 6971098Abstract: Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received.Type: GrantFiled: June 27, 2001Date of Patent: November 29, 2005Assignee: Intel CorporationInventors: Manoj Khare, Akhilesh Kumar, Ioannis Schoinas, Lily Pao Looi
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Patent number: 6810467Abstract: An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the system's nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line.Type: GrantFiled: August 21, 2000Date of Patent: October 26, 2004Assignee: Intel CorporationInventors: Manoj Khare, Faye A. Briggs, Kai Cheng, Lily Pao Looi
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Publication number: 20040117561Abstract: Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.Type: ApplicationFiled: December 17, 2002Publication date: June 17, 2004Inventors: Tuan M. Quach, Lily Pao Looi, Kai Cheng
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Publication number: 20030005167Abstract: Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Inventors: Manoj Khare, Akhilesh Kumar, Loannis Schoinas, Lily Pao Looi