Patents by Inventor Lim Chieh

Lim Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock gated pipeline stages
    Publication number: 20070074054
    Abstract: Methods and apparatus are described that gate a clock signal from pipeline stages of a processor. In one embodiment, gated clock logic determines which pipeline stages are active and which pipeline stages are idle. The gated clock logic permits a clock signal to drive active stages and gates the clock signal from driving idle stages.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Inventor: Lim Chieh
  • Queue structure with validity vector and order array
    Publication number: 20050289305
    Abstract: According to some embodiments, a queue structure includes a validity vector and an order array.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 29, 2005
    Inventor: Lim Chieh