Abstract: A frequency divider having an input frequency divider, an edge counter, and an output generator. The input frequency divider generates an intermediate signal having a frequency of fi from an input signal having a frequency fin, wherein fin=2fi. The edge counter generates a value equal to the number of edges in the intermediate signal that have occurred since a reset signal was generated. The output generator generates an output signal when the edge counter value reaches a value Q and generates the reset signal. In one embodiment, the edge counter includes a positive edge counter that counts the number of positive going transitions in the intermediate signal since the reset signal, a negative edge counter that counts the number of negative going transitions in the intermediate signal, and an adder that generates the sum of the positive and negative count values.