Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.

Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.

Abstract: A method for designing artificial impedance surfaces is disclosed. The method involves matching impedance component values required for a given far-field radiation pattern (determined, for example, by holographic means) with measured or simulated impedance component values for the units of a lattice of conductive structures used to create an artificial impedance surface, where the units of the lattice have varied geometry. For example, a unit could be a square conductive structure with a slice (removed or missing material) through it. The measured or simulated impedance components are determined by measuring wavevector values for test surfaces in three or more directions over any number of test surfaces, where each unit of a given test surface has the same geometric shape and proportions as all of the other units of that test surface, but each test surface has some form of variation in the unit geometry from the other test surfaces. These test measurements create a table of geometry vs.

Abstract: Described is a scalable quantum computer that includes at least two classical to quantum interface devices, with each being connected to a distinct quantum processing unit (QPU). An Einstein-Podolsky-Rosen pair generator (EPRPG) is included for generating an entangled Einstein-Podolsky-Rosen pair that is sent to the QPUs. Each QPU is quantumly connected with the EPRPG and is configured to receive a mobile qubit from the EPRPG and perform a sequence of operations such that the mobile qubit interacts with a source qubit when a teleportation algorithm is initiated, leaving a second mobile qubit in the original quantum state of the source qubit.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: An artificial impedance structure and a method for manufacturing same. The structure contains a dielectric layer having generally opposed first and second surfaces, a conductive layer disposed on the first surface, and a plurality of conductive structures disposed on the second surface to provide a preselected impedance profile along the second surface.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: A method for guiding waves over objects, a method for improving a performance of an antenna, and a method for improving a performance of a radar are disclosed. The methods disclosed teach how an impedance structure can be used to guide waves over objects.