Patents by Inventor Lim Peng Soon

Lim Peng Soon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7419855
    Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 2, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Shaw Wei Lee, Nghia Thuc Tu, Santhiran S/O Nadarajah, Lim Peng Soon
  • Patent number: 7187075
    Abstract: Techniques for reducing the mechanical stress imposed upon semiconductor dice by protective molding compounds during times of temperature fluctuation. A thermoplastic material is attached to a top surface of a die to relieve the stress. The thermoplastic material serves as a cushion between the die and the molding compound when the components expand and contract. The thermoplastic material can be shaped such that it does not cover bond pads on the surface of a die.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: March 6, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Tan Eng Hwa, Lim Peng Soon, Santhiran S/O Nadarajah, Ong Sze Yan
  • Patent number: 7161232
    Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: January 9, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Shaw Wei Lee, Nghia Thuc Tu, Santhiran S/O Nadarajah, Lim Peng Soon
  • Patent number: 6933223
    Abstract: A wire bonding technique for manufacturing semiconductor devices that results in a bonded wire having a small loop height. The wire bonding technique involves a capillary tool that ball bonds a wire to a first contact point, then moves upwards, and then towards a second contact point to which the wire will be attached. The capillary tool only moves towards the second contact point in the lateral direction. The height of the wire loop of the bonded wires can be controlled to have desired wire loop heights. The bonding technique can be used in semiconductor devices with stacked dice and in devices where a die and a contact lead are approximately at the same height.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: August 23, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Lim Peng Soon, Chan Peng Yeen