Abstract: A protective film, a method for fabricating the same, and a display device are provided. The protective film is configured to be applied to a self-luminous display panel. The protective film includes a quantum dot color conversion layer, a first base substrate, a polymer dispersed liquid crystal layer, and a second base substrate. Scattering of liquid crystal monomers in the polymer dispersed liquid crystal layer does not affect brightness of light in a front view direction, and can improve intensity of an emitted light, thereby effectively improving luminous efficiency of a display panel and user experiences.

Abstract: A scan driving circuit and a display panel are disclosed. A scan driving unit includes a pull-up control circuit configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node. A first reset circuit receives an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage. A pull-down holding circuit receives a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node. A pull-down circuit receives a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node. A pull-up circuit receives the first clock signal to output a stage transmission signal and a scan driving signal of the current stage.

Abstract: A scan driving circuit and a display panel are disclosed. A scan driving unit includes a pull-up control circuit configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node. A first reset circuit receives an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage. A pull-down holding circuit receives a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node. A pull-down circuit receives a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node. A pull-up circuit receives the first clock signal to output a stage transmission signal and a scan driving signal of the current stage.

Abstract: The present disclosure relates to a gate driver on array (GOA) circuit and a liquid crystal display (LCD). The GOA circuit includes a plurality of cascaded-connected GOA units connected, and the GOA unit at N-th level includes: a pull-up controlling module, a pull-up module, a down-transfer module, a bootstrap capacitor module, a pull-down maintaining module, a pull-down module and a controlling module. The controlling module respectively connects with the pull-down maintaining module and the adjacent GOA unit, and the controlling module is configured to accelerate a pull-down speed of the pull-down maintaining module by increasing a discharge path of the pull-down maintaining module on the GOA unit at the next level. As such, the response speed of the pull-down maintaining module may be improved, so as to improve the performance of the pull-down maintaining module.

Abstract: A GOA circuit applied in an LCD is provided. The GOA unit circuit includes cascaded GOA unit circuits. An Nth-stage GOA unit circuit includes a pull-up control circuit, a pull-up circuit, a downlink circuit, a bootstrap capacitance circuit, a pull-down holding circuit and a pull-down circuit. The pull-up control circuit couples to an (N?2)th-stage cascade signal and an (N?2)th-stage scanning signal. The pull-up circuit and the downlink circuit are connected a clock signal. The pull-down holding circuit couples to a first control signal. The pull-down circuit couples to an (N+2)th-stage cascade signal. By the GOA circuit, a set of pull-down holding circuit is adopted by the present disclosure, thereby reducing the number of transistors for use and further decreasing the difficulty in designing an LCD with a narrow bezel or without a bezel.

Abstract: The present disclosure relates to a gate driver on array (GOA) circuit and a liquid crystal display (LCD). The GOA circuit includes a plurality of cascaded-connected GOA units connected, and the GOA unit at N-th level includes: a pull-up controlling module, a pull-up module, a down-transfer module, a bootstrap capacitor module, a pull-down maintaining module, a pull-down module and a controlling module. The controlling module respectively connects with the pull-down maintaining module and the adjacent GOA unit, and the controlling module is configured to to accelerate a pull-down speed of the pull-down maintaining module by increasing a discharge path of the pull-down maintaining module on the GOA unit at the next level. As such, the response speed of the pull-down maintaining module may be improved, so as to improve the performance of the pull-down maintaining module.

Abstract: A method for compensating resistance of signal lines of gate driving circuits and the liquid crystal panel applying the method are provided. The method includes: (1) providing a TFT substrate having a GOA area arranged thereon, the GOA area comprises a plurality of GOA units, each of the GOA units comprises a plurality of GOA modules electrically connects to one pull-line; (2) providing a control system board electrically connecting to the GOA modules via the pull-lines; and (3) adjusting the resistance between the control system board and the GOA modules such that the clock signals provided from the control system board to the GOA modules within the same GOA unit is the same. As such, the delays of the gate driving signals are the same, and the charging rate of the two adjacent pixel rows are the same. In this way, the gray scales of the two adjacent pixel rows are the same, not only the stripes are avoided but also the display performance is enhanced.

Abstract: A method for compensating resistance of signal lines of gate driving circuits and the liquid crystal panel applying the method are provided. The method includes: (1) providing a TFT substrate having a GOA area arranged thereon, the GOA area comprises a plurality of GOA units, each of the GOA units comprises a plurality of GOA modules electrically connects to one pull-line; (2) providing a control system board electrically connecting to the GOA modules via the pull-lines; and (3) adjusting the resistance between the control system board and the GOA modules such that the clock signals provided from the control system board to the GOA modules within the same GOA unit is the same. As such, the delays of the gate driving signals are the same, and the charging rate of the two adjacent pixel rows are the same. In this way, the gray scales of the two adjacent pixel rows are the same, not only the stripes are avoided but also the display performance is enhanced.

Abstract: The present invention provides a gate driver on array circuit. The gate driver on array circuit comprises: multiple gate driver on array units connected in cascade. The n-th gate driver on array unit of the gate driver on array circuit comprises a (n?2)-th signal input terminal 21, a (n+2)-th signal input terminal 22, a clock signal first input terminal 23, a clock signal second input terminal 24, a first low-level input terminal 25, a second low-level input terminal 26, a first output terminal 27 and a second output terminal 28. The n-th gate driver on array unit further comprises: a pulling-up driving unit 32, a pulling-up unit 34, a first to a third pulling-down unit 36, 37, 38. The present invention adds a second low-level signal, which uses the second low-level to decrease the voltage difference (Vgs) between the gate and the source of the thin film transistor of the first output terminal, so that the leakage current of the thin film transistor is less and can be controlled precisely.

Abstract: The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54).

Abstract: The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54).

Abstract: The present invention provides a gate driver on array circuit. The gate driver on array circuit comprises: multiple gate driver on array units connected in cascade. The n-th gate driver on array unit of the gate driver on array circuit comprises a (n?2)-th signal input terminal 21, a (n+2)-th signal input terminal 22, a clock signal first input terminal 23, a clock signal second input terminal 24, a first low-level input terminal 25, a second low-level input terminal 26, a first output terminal 27 and a second output terminal 28. The n-th gate driver on array unit further comprises: a pulling-up driving unit 32, a pulling-up unit 34, a first to a third pulling-down unit 36, 37, 38. The present invention adds a second low-level signal, which uses the second low-level to decrease the voltage difference (Vgs) between the gate and the source of the thin film transistor of the first output terminal, so that the leakage current of the thin film transistor is less and can be controlled precisely.