Patents by Inventor Limin Weng
Limin Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10096588Abstract: A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.Type: GrantFiled: September 30, 2017Date of Patent: October 9, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Wenjiang Zeng, Limin Weng
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Publication number: 20180026025Abstract: A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.Type: ApplicationFiled: September 30, 2017Publication date: January 25, 2018Applicant: Alpha and Omega Semiconductor IncorporatedInventors: MADHUR BOBDE, WENJIANG ZENG, LIMIN WENG
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Patent number: 9793254Abstract: A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.Type: GrantFiled: December 9, 2014Date of Patent: October 17, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Wenjiang Zeng, Limin Weng
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Publication number: 20170141097Abstract: A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.Type: ApplicationFiled: December 9, 2014Publication date: May 18, 2017Inventors: Madhur Bobde, Wenjiang Zeng, Limin Weng
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Patent number: 9252265Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: GrantFiled: March 17, 2015Date of Patent: February 2, 2016Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Gary Chen, Jongoh Kim, John Chen
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Publication number: 20150194522Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: ApplicationFiled: March 17, 2015Publication date: July 9, 2015Inventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Gary Chen, Jongoh Kim, John Chen
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Patent number: 8994101Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: GrantFiled: April 18, 2013Date of Patent: March 31, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Jongoh Kim, John Chen
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Patent number: 8835977Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.Type: GrantFiled: December 19, 2012Date of Patent: September 16, 2014Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
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Publication number: 20140167101Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
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Patent number: 8580676Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.Type: GrantFiled: January 30, 2012Date of Patent: November 12, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hong Chang, John Chen, Limin Weng, Wenjun Li
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Publication number: 20130228860Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: ApplicationFiled: April 18, 2013Publication date: September 5, 2013Inventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Gary Chen, Jongoh Kim, John Chen
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Patent number: 8431457Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: GrantFiled: March 11, 2010Date of Patent: April 30, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Gary Chen, Jongoh Kim, John Chen
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Patent number: 8338854Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.Type: GrantFiled: March 31, 2009Date of Patent: December 25, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
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Publication number: 20120129328Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventors: Hong Chang, John Chen, Limin Weng, Wenjun Li
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Patent number: 8138605Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.Type: GrantFiled: October 26, 2009Date of Patent: March 20, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Hong Chang, John Chen, Limin Weng, Wenjun Li
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Publication number: 20110220990Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: ApplicationFiled: March 11, 2010Publication date: September 15, 2011Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Gary Chen, Jongoh Kim, John Chen
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Publication number: 20110095361Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventors: Hong Chang, John Chen, Limin Weng, Wenjun Li
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Patent number: 7863995Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.Type: GrantFiled: April 1, 2008Date of Patent: January 4, 2011Assignee: Alpha & Omega Semiconductor Ltd.Inventors: Moses Ho, Madhur Bobde, Mike Chang, Limin Weng
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Publication number: 20100244090Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
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Publication number: 20080310065Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.Type: ApplicationFiled: April 1, 2008Publication date: December 18, 2008Inventors: Moses Ho, Madhur Bobde, Mike Chang, Limin Weng