Patents by Inventor Limor Elizov

Limor Elizov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Modifying a circuit design
    Patent number: 10568203
    Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ofer Geva, Shiran Raz, Limor Elizov, Yaniv Maroz
  • Modifying a Circuit Design
    Publication number: 20180359852
    Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.
    Type: Application
    Filed: December 20, 2017
    Publication date: December 13, 2018
    Inventors: Ofer Geva, Shiran Raz, Limor Elizov, Yaniv Maroz
  • Modifying a Circuit Design
    Publication number: 20180359851
    Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventors: Ofer Geva, Shiran Raz, Limor Elizov, Yaniv Maroz