Abstract: A package structure and method for forming the same are provided. The package structure includes a top interposer formed over a substrate, and a first die formed over the top interposer. The first die includes an optical package structure, and the optical package structure includes first optical components. The first die also includes an electronic die bonded to the optical package structure to form a hybrid bonding structure. The hybrid bonding structure includes a metal-to-metal bonding and dielectric-to-dielectric bonding. The package structure includes an optical die adjacent to the first die, and the top interposer is shared by the optical die and the first die.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Abstract: The method includes receiving a semiconductor structure including a first surface, the first surface including a uniform material composition of ruthenium (Ru), selecting a first polishing slurry including a first abrasive component of titanium oxide and a first amine-based alkaline component of ammonium hydroxide, selecting a second polishing slurry including a second abrasive component of silicon oxide, a second amine-based alkaline component of hydroxyamine, and a non-amine alkaline component, polishing the first surface with the first polishing slurry until a second surface is exposed, the second surface including a conductive material and a dielectric material, and polishing the second surface with the second polishing slurry.

Abstract: In-situ defect count detection in post chemical mechanical polishing (post-CMP) is provided. Post-CMP is performed, in-situ and according to a recipe, on a surface of a semiconductor wafer within a post-CMP chamber. A light signal is scanned over a target area of the surface of the semiconductor wafer and a reflected light signal reflected from the target area is detected. A defect count of defects present in the target area is determined based on the reflected light signal reflected from the target area.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: An intelligent meeting assistance system and a method for generating meeting minutes are provided. The intelligent meeting assistance system includes an image capturing device and an image analyzing device. The image capturing device is configured to capture an image displayed by an interactive device during a meeting. The image analyzing device is coupled to the image capturing device, and is configured to execute an image analysis process on the image to generate first meeting minutes that record image content.

Abstract: Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.

Abstract: Optical devices and methods of manufacture are presented in which glass interposers are incorporated with optical devices. In some embodiments a method includes forming a first optical package and then bonding the first optical package to a first glass interposer. The first glass interposer may then be connected to a second interposer.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.

Abstract: An antenna-in-package with a heat dissipation structure includes a circuit board, an antenna substrate, a chip, a plurality of heat dissipation fins, a chassis, and dielectric fluid. The circuit board has a first surface and a second surface opposite to the first surface. The antenna substrate is disposed above the first surface of the circuit board. The chip is disposed between the antenna substrate and the first surface of the circuit board and is electrically connected to the antenna substrate. The plurality of heat dissipation fins protrude from the second surface of the circuit board. The chassis encapsulates the circuit board, the antenna substrate, the chip, and the plurality of heat dissipation fins. The dielectric fluid circulates and flows in the chassis through a cooling circulation device and is in direct contact with the plurality of heat dissipation fins.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an optical device is provided that includes an optical package having a first surface and a second surface opposite the first surface, a laser die package having a third surface and a fourth surface opposite the third surface, wherein the first surface is planar with the third surface and the second surface is planar with the fourth surface, a first silicon support attached to both the second surface and the fourth surface, and an interposer attached to both the first surface and the third surface, wherein the interposer is free of a silicon substrate.

Abstract: Optical devices and methods of manufacture are presented in which a resonant ring is incorporated with a optical device on an interposer substrate. The material for the resonant ring may be a material that can trigger second order non-linearity in received light or a material that can trigger third order non-linearity without electrical driving mechanisms.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.