Patents by Inventor Lin-Chih Huang
Lin-Chih Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11756883Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.Type: GrantFiled: July 13, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11728296Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.Type: GrantFiled: October 19, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20210050316Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.Type: ApplicationFiled: October 19, 2020Publication date: February 18, 2021Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20200343176Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10811374Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.Type: GrantFiled: January 5, 2018Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10714423Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.Type: GrantFiled: November 2, 2017Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10290604Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.Type: GrantFiled: December 11, 2017Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
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Patent number: 10217687Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.Type: GrantFiled: March 16, 2018Date of Patent: February 26, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tien-Chung Yang, Lin-Chih Huang, Hsien-Wei Chen, An-Jhih Su, Li-Hsien Huang
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Patent number: 10157866Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.Type: GrantFiled: June 5, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20180211895Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.Type: ApplicationFiled: March 16, 2018Publication date: July 26, 2018Inventors: TIEN-CHUNG YANG, LIN-CHIH HUANG, HSIEN-WEI CHEN, AN-JHIH SU, LI-HSIEN HUANG
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Publication number: 20180145022Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.Type: ApplicationFiled: November 2, 2017Publication date: May 24, 2018Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20180145046Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.Type: ApplicationFiled: January 5, 2018Publication date: May 24, 2018Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20180114770Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.Type: ApplicationFiled: December 11, 2017Publication date: April 26, 2018Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
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Patent number: 9953920Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.Type: GrantFiled: April 13, 2015Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 9929069Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.Type: GrantFiled: December 15, 2016Date of Patent: March 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tien-Chung Yang, Lin-Chih Huang, Hsien-Wei Chen, An-Jhih Su, Li-Hsien Huang
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Patent number: 9842825Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.Type: GrantFiled: September 5, 2014Date of Patent: December 12, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
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Patent number: 9831177Abstract: An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material.Type: GrantFiled: August 17, 2015Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20170271287Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 9748190Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.Type: GrantFiled: January 23, 2015Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Tasi-Jung Wu, Wen-Chih Chiou
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Patent number: 9679859Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.Type: GrantFiled: January 8, 2016Date of Patent: June 13, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou