Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.

Abstract: A method for fabricating a self-aligned contact hole in accordance with the present invention is disclosed. First a conductive layer, a silicon oxide layer, and a first silicon nitride layer are formed on a silicon substrate. Next, the first silicon nitride layer, the silicon oxide layer, and the conductive layer are etched to form a trench. Then, a BPSG layer is formed over the first silicon nitride layer. A photoresist layer having an opening is defined. Then, using the photoresist layer as the masking layer, a part of BPSG layer is etched to form a self-aligned hole. Next, the photoresist layer is removed. Afterward, a second silicon nitride layer is formed and etched back to form a spacer.

Abstract: A method for fabricating a LOCOS isolation in accordance with the present invention, involves first forming a masking layer on the active region of a silicon substrate. Next, the masking layer is used as the etching mask and the silicon substrate is etched to form a recess. Then, a thin nitride layer is formed on the masking layer and the recess. Afterwards, a polysilicon layer is deposited on the thin nitride layer. Then, an etching process is applied to etch back the polysilicon and the thin nitride layer, thereby exposing the upper surface of the masking layer. Next, a LOCOS isolation is grown above the recess.

Abstract: A method for fabricating LOCOS isolation having a planar surface. The method utilizes a polysilicon spacer to prevent bird beak. The method adds the steps of forming a polishing stop layer and removing said edge-protrusion portion of the local oxide by chemical mechanical polishing.