Abstract: An electrical receptacle connector includes an insulated housing, a plurality of upper-row receptacle terminals, and a plurality of lower-row receptacle terminals. The insulated housing includes a base portion. Each of the upper-row receptacle terminals includes a tail portion protruded from the base portion. Each of the lower-row receptacle terminals includes a tail portion protruded from the base portion. The tail portions of the upper-row receptacle terminals and the tail portions of the lower-row receptacle terminals are protruded from the base portion, aligned into a line, and spaced from each other.

Abstract: An electrical receptacle connector includes an insulated housing, a plurality of upper-row receptacle terminals, and a plurality of lower-row receptacle terminals. The insulated housing includes a base portion. Each of the upper-row receptacle terminals includes a tail portion protruded from the base portion. Each of the lower-row receptacle terminals includes a tail portion protruded from the base portion. The tail portions of the upper-row receptacle terminals and the tail portions of the lower-row receptacle terminals are protruded from the base portion, aligned into a line, and spaced from each other.

Abstract: An apparatus comprising an interface and a control circuit. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to determine if a read disturb has occurred. If the read disturb has occurred, the control circuit may (a) determine a size of a group of the read/write operations and (b) write all of the group of the read/write operations to one of a plurality of memory modules of the memory.

Abstract: Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size.

Abstract: An apparatus comprising an interface and a control circuit. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to determine if a read disturb has occurred. If the read disturb has occurred, the control circuit may (a) determine a size of a group of the read/write operations and (b) write all of the group of the read/write operations to one of a plurality of memory modules of the memory.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to (i) determine if a read disturb has occurred, and (ii) if the read disturb has occurred, the controller (a) determines a size of the group of read/write operations, and (b) writes all of the group of read/write operations to one of the memory modules.

Abstract: Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to (i) determine if a read disturb has occurred, and (ii) if the read disturb has occurred, the controller (a) determines a size of the group of read/write operations, and (b) writes all of the group of read/write operations to one of the memory modules.

Abstract: The present invention provides methods for identification of agents that modulate NF-?B activity through modulation of the acetylation and deacetylation of the RelA subunit of NF-?B.

Abstract: The present invention provides methods for identification of agents that modulate NF-&kgr;B activity through modulation of the acetylation and deacetylation of the RelA subunit of NF-&kgr;B.