Patents by Inventor Lin-feng Chen
Lin-feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11225507Abstract: The disclosure provides a class of pH-sensitive, helix/random conformation switchable antimicrobial polypeptide (HRS-AMP) compositions as a single agent to selectively kill bacteria (e.g., H. pylori) under acidic condition in the stomach with diminished bacterial resistance compared to currently used antibiotics. Methods of treating bacterial infections in the stomach are also provided.Type: GrantFiled: January 25, 2018Date of Patent: January 18, 2022Assignee: The Board of Trustees of the University of IllinoisInventors: Jianjun Cheng, Lin-Feng Chen, Menghua Xiong, Yan Bao
-
Publication number: 20200399319Abstract: The disclosure provides a class of pH-sensitive, helix/random conformation switchable antimicrobial polypeptide (HRS-AMP) compositions as a single agent to selectively kill bacteria (e.g., H. pylori) under acidic condition in the stomach with diminished bacterial resistance compared to currently used antibiotics. Methods of treating bacterial infections in the stomach are also provided.Type: ApplicationFiled: January 25, 2018Publication date: December 24, 2020Applicant: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOISInventors: Jianjun Cheng, Lin-Feng Chen, Menghua Xiong, Yan Bao
-
Patent number: 9502839Abstract: An electrical receptacle connector includes an insulated housing, a plurality of upper-row receptacle terminals, and a plurality of lower-row receptacle terminals. The insulated housing includes a base portion. Each of the upper-row receptacle terminals includes a tail portion protruded from the base portion. Each of the lower-row receptacle terminals includes a tail portion protruded from the base portion. The tail portions of the upper-row receptacle terminals and the tail portions of the lower-row receptacle terminals are protruded from the base portion, aligned into a line, and spaced from each other.Type: GrantFiled: December 11, 2015Date of Patent: November 22, 2016Assignee: ADVANCED-CONNECTEK INC.Inventors: Yu-Lun Tsai, Pin-Yuan Hou, Chung-Fu Liao, Ya-Fen Kao, Rui Su, Lin-Feng Chen
-
Publication number: 20160181743Abstract: An electrical receptacle connector includes an insulated housing, a plurality of upper-row receptacle terminals, and a plurality of lower-row receptacle terminals. The insulated housing includes a base portion. Each of the upper-row receptacle terminals includes a tail portion protruded from the base portion. Each of the lower-row receptacle terminals includes a tail portion protruded from the base portion. The tail portions of the upper-row receptacle terminals and the tail portions of the lower-row receptacle terminals are protruded from the base portion, aligned into a line, and spaced from each other.Type: ApplicationFiled: December 11, 2015Publication date: June 23, 2016Inventors: Yu-Lun Tsai, Pin-Yuan Hou, Chung-Fu Liao, Ya-Fen Kao, Rui SU, Lin-Feng CHEN
-
Patent number: 9342246Abstract: An apparatus comprising an interface and a control circuit. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to determine if a read disturb has occurred. If the read disturb has occurred, the control circuit may (a) determine a size of a group of the read/write operations and (b) write all of the group of the read/write operations to one of a plurality of memory modules of the memory.Type: GrantFiled: June 18, 2015Date of Patent: May 17, 2016Assignee: Seagate Technology LLCInventors: Zhiqing Zhang, Yuan Chen, Yun Shun Tan, Xing Hui Duan, Lin Feng Chen
-
Patent number: 9235346Abstract: Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size.Type: GrantFiled: December 3, 2013Date of Patent: January 12, 2016Assignee: Avago Technologies General IP (Singapore) PTE. LTD.Inventors: Leonid Baryudin, Zhiqing Zhang, Xin Song, Yun Shun Tan, Lin Feng Chen
-
Publication number: 20150286407Abstract: An apparatus comprising an interface and a control circuit. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to determine if a read disturb has occurred. If the read disturb has occurred, the control circuit may (a) determine a size of a group of the read/write operations and (b) write all of the group of the read/write operations to one of a plurality of memory modules of the memory.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Zhiqing Zhang, Yuan Chen, Yun Shun Tan, Xing Hui Duan, Lin Feng Chen
-
Patent number: 9092310Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to (i) determine if a read disturb has occurred, and (ii) if the read disturb has occurred, the controller (a) determines a size of the group of read/write operations, and (b) writes all of the group of read/write operations to one of the memory modules.Type: GrantFiled: April 2, 2013Date of Patent: July 28, 2015Assignee: Seagate Technology LLCInventors: Zhiqing Zhang, Yuan Chen, Yun Shun Tan, Xing Hui Duan, Lin Feng Chen
-
Publication number: 20150074328Abstract: Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size.Type: ApplicationFiled: December 3, 2013Publication date: March 12, 2015Applicant: LSI CorporationInventors: Leonid Baryudin, Zhiqing Zhang, Xin Song, Yun Shun Tan, Lin Feng Chen
-
Publication number: 20140281281Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to (i) determine if a read disturb has occurred, and (ii) if the read disturb has occurred, the controller (a) determines a size of the group of read/write operations, and (b) writes all of the group of read/write operations to one of the memory modules.Type: ApplicationFiled: April 2, 2013Publication date: September 18, 2014Applicant: LSI CorporationInventors: Zhiqing Zhang, Yuan Chen, Yun Shun Tan, Xing Hui Duan, Lin Feng Chen
-
Patent number: 7081343Abstract: The present invention provides methods for identification of agents that modulate NF-?B activity through modulation of the acetylation and deacetylation of the RelA subunit of NF-?B.Type: GrantFiled: June 18, 2001Date of Patent: July 25, 2006Assignee: The Regents of the University of CaliforniaInventors: Lin-feng Chen, Wolfgang Fischle, Eric M. Verdin, Warner C. Greene
-
Publication number: 20020193284Abstract: The present invention provides methods for identification of agents that modulate NF-&kgr;B activity through modulation of the acetylation and deacetylation of the RelA subunit of NF-&kgr;B.Type: ApplicationFiled: June 18, 2001Publication date: December 19, 2002Inventors: Lin-feng Chen, Wolfgang Fischle, Eric M. Verdin, Warner C. Greene