Abstract: Examples of integrated circuit (IC) structures with a merged nanoribbon-based transistor fabricated using NP ratio tuning techniques are described herein. In one example, an IC structure may include a different gate electrode material around a wider portion of the nanoribbon than around a narrower portion of the nanoribbon. In another example, a wider portion of a nanoribbon may have a smaller thickness than a narrower portion of the nanoribbon. In another example, a gate dielectric material may be thicker around a wider portion of the nanoribbon than around a narrower portion of the nanoribbon. One or more of these techniques may be used to adjust the strength of a nanoribbon (e.g., the P-type nanoribbon) to achieve a desired NP ratio with or without using a jog in the IC circuit design.

Abstract: Disclosed herein are integrated circuit (IC) structures with nanoribbon transistors and C-clamp source and/or drain (S/D) contacts, and related methods and devices. In one aspect, an example IC structure may include a transistor having a channel portion in a nanoribbon, and a conductive contact to a region of the transistor, where the region is one of a source region or a drain region of the transistor and where, in a cross-sectional side view of the IC structure, the conductive contact has a C-shape.

Abstract: Disclosed herein are IC structures with nanoribbon transistors and S/D contacts at opposite sides of nanoribbons, and related methods and devices. An example IC structure includes a nanoribbon; a transistor including a channel portion in a portion of the nanoribbon, a first S/D region, and a second S/D region; a first conductive contact in conductive contact with the first S/D region, the first conductive contact being at the front side of the channel portion; a second conductive contact in conductive contact with the second S/D region, the second conductive contact being at the back side of the channel portion; and an insulator structure in contact with the first S/D region, the insulator structure being at the back side of the channel portion, where, in a cross-sectional side view of the IC structure, a shape of the insulator structure at an interface with the first S/D region is convex.

Abstract: A tertiary frequency modulation method for a power system, AGC based on power plant input performs active power regulation for tertiary frequency modulation in different modes in power plants in case of secondary frequency modulation failure of the power system and unidirectional deviation of grid frequency from rated frequency for a period: perform tertiary frequency modulation based on the reserved capacity of the secondary frequency modulation or the regulation amount of primary frequency modulation or random parameters. The invention relates to tertiary frequency modulation whose action sequence is later than that of the primary frequency modulation and the secondary frequency modulation to realize astatic frequency regulation.

Abstract: Transistor structures with a dielectric trench plug below source and drain semiconductor material. Following frontside processing, a workpiece may be inverted and backside interconnect metallization fabricated. The dielectric trench plug can electrically insulate the backside interconnect metallization from source and drain semiconductor material. In some examples, a dielectric trench plug is formed during frontside processing, backfilling a trench in subfin semiconductor material prior to the deposition of source and drain semiconductor material. In other examples, a dielectric trench plug is formed during backside processing. When source or drain semiconductor material is exposed with a backside planarization polish, a recess may be etched in the exposed semiconductor material and the recess backfilled with the dielectric trench plug.

Abstract: Integrated circuit (IC) structures with lined source or drain regions, as well as related method and devices, are disclosed. In one aspect, an IC structure may include a channel region of a transistor, a first region proximate to a first end of the channel region, and a second region proximate to a second end of the channel region, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor, the first region includes a liner material and a fill material, the liner material is laterally between the fill material and the channel region, and a material composition of the liner material is different from a material composition of the fill material.

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Described herein are nanoribbon transistors and processes for forming nanoribbon transistors that include a nitride liner to protect the channel material during an oxide anneal. An oxide may be used to fill trenches between stacks of nanoribbons; the oxide is annealed, and then the oxide is recessed, forming isolation regions. Source and drain regions are formed over the isolation regions. In the resulting devices, the isolation regions have a liner layer that includes nitrogen. An additional oxide liner may be around the nitride liner.

Abstract: Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.

Abstract: Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned fork-last backbones. In an example, an integrated circuit structure includes a dielectric backbone. A first vertical stack of nanowires is laterally adjacent to and in contact with a first side of the dielectric backbone. A first epitaxial source or drain structure is at an end of the first vertical stack of nanowires. A second vertical stack of nanowires is laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side. A second epitaxial source or drain structure is at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to but not merged with the first epitaxial source or drain structure.

Abstract: Integrated circuit structures having zero diffusion break and wrap-around contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure having a cut extending there through to separate a first portion of the epitaxial source or drain structure from a second portion of the epitaxial source or drain structure.

Abstract: Integrated circuit structures having selectively grown metal gate structures are described. For example, a structure includes a first vertical arrangement of horizontal nanowires or fin laterally spaced apart from a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, the first gate stack having a first conductive layer over a first gate dielectric, and a first conductive fill over the first conductive layer. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, the second gate stack having a second conductive layer over a second gate dielectric, and a second conductive fill over the second conductive layer and over the first conductive fill. A portion of the second conductive fill is laterally adjacent to the first conductive fill without having the second conductive layer there between.

Abstract: Integrated circuit structures having differentiated dielectric boundary walls, and methods of fabricating integrated circuit structures having differentiated dielectric boundary walls, are described. For example, an integrated circuit structure includes a sub-fin in a trench isolation structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric boundary wall is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a portion of the trench isolation structure. The dielectric boundary wall has a composition including a metal and oxygen. A dielectric gate plug is on the dielectric boundary wall.

Abstract: Integrated circuit (IC) devices having stacked, complementary transistors with channels of different compositions. A device includes transistors with first and second groups of nanoribbons vertically aligned in a stack of nanoribbon channels coupling first and second sources and drains, and one of the first and second nanoribbons has a semiconductor element absent from the other. The first and second groups of nanoribbons extend between first and second spacers, which may have different compositions. First and second hardmasks with different compositions may be used process the first and second groups of nanoribbons separately. A masking layer having the composition of one of the first and second nanoribbons may mask the other of the first and second nanoribbons.

Abstract: An nucleic acid integrated detection method is provided, the method includes separating a lysis solution, a cleaning solution and a reaction solution in a detection reagent tube by providing a plurality of separation plugs in an over-under arrangement and disposing a hydrophobic layer in liquid or solid phase on each separation plug; adding a sample into the lysis solution; extracting nucleic acid in the sample using magnetic nanobeads; and then driving the magnetic nanobeads carrying the nucleic acid to sequentially pass through each hydrophobic layer along a magnetic bead channel and into the cleaning solution and the reaction solution to realize a cleaning and amplification for the nucleic acid, and finally, detecting the nucleic acid of the sample by an external device using an optical detection method, thus realizing a plurality of steps of nucleic acid extraction, cleaning and amplification reactions in the same detection reagent tube.

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Contact over active gate (COAG) structures with widened and lower capacitance gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using widened and lower capacitance gate insulating cap layers, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is coupled to the vertical stack of horizontal nanowires or the fin. A gate stack is over the vertical stack of horizontal nanowires or the fin, the gate stack including a gate dielectric and a gate electrode. A gate dielectric spacer is along sides of the gate stack. A gate insulating cap structure is on the gate stack and extending laterally beyond the gate stack, the gate insulating cap structure vertically over the gate dielectric spacer, and the gate insulating cap structure including a dielectric liner and a dielectric fill.

Abstract: Integrated circuit structures having backside isolation structures are described. An integrated circuit structure includes a first stack of nanowires or fin above a backside surface. A second stack of nanowires or fin is above the backside surface and is laterally spaced apart from the first stack of nanowires or fin. A gate electrode is around the first and second stacks of nanowires or fins. A first epitaxial source or drain structure is at an end of the first stack of nanowires or fin and at a side of the gate electrode. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin and at the side of the gate electrode. A dielectric structure extends from the backside surface into the gate electrode and laterally between the first epitaxial source or drain structure and the second epitaxial source or drain structure.