Abstract: Described herein are nanoribbon transistors and processes for forming nanoribbon transistors that include a nitride liner to protect the channel material during an oxide anneal. An oxide may be used to fill trenches between stacks of nanoribbons; the oxide is annealed, and then the oxide is recessed, forming isolation regions. Source and drain regions are formed over the isolation regions. In the resulting devices, the isolation regions have a liner layer that includes nitrogen. An additional oxide liner may be around the nitride liner.

Abstract: Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.

Abstract: Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned fork-last backbones. In an example, an integrated circuit structure includes a dielectric backbone. A first vertical stack of nanowires is laterally adjacent to and in contact with a first side of the dielectric backbone. A first epitaxial source or drain structure is at an end of the first vertical stack of nanowires. A second vertical stack of nanowires is laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side. A second epitaxial source or drain structure is at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to but not merged with the first epitaxial source or drain structure.

Abstract: Integrated circuit structures having zero diffusion break and wrap-around contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure having a cut extending there through to separate a first portion of the epitaxial source or drain structure from a second portion of the epitaxial source or drain structure.

Abstract: Integrated circuit structures having selectively grown metal gate structures are described. For example, a structure includes a first vertical arrangement of horizontal nanowires or fin laterally spaced apart from a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, the first gate stack having a first conductive layer over a first gate dielectric, and a first conductive fill over the first conductive layer. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, the second gate stack having a second conductive layer over a second gate dielectric, and a second conductive fill over the second conductive layer and over the first conductive fill. A portion of the second conductive fill is laterally adjacent to the first conductive fill without having the second conductive layer there between.

Abstract: Integrated circuit structures having differentiated dielectric boundary walls, and methods of fabricating integrated circuit structures having differentiated dielectric boundary walls, are described. For example, an integrated circuit structure includes a sub-fin in a trench isolation structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric boundary wall is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a portion of the trench isolation structure. The dielectric boundary wall has a composition including a metal and oxygen. A dielectric gate plug is on the dielectric boundary wall.

Abstract: Integrated circuit (IC) devices having stacked, complementary transistors with channels of different compositions. A device includes transistors with first and second groups of nanoribbons vertically aligned in a stack of nanoribbon channels coupling first and second sources and drains, and one of the first and second nanoribbons has a semiconductor element absent from the other. The first and second groups of nanoribbons extend between first and second spacers, which may have different compositions. First and second hardmasks with different compositions may be used process the first and second groups of nanoribbons separately. A masking layer having the composition of one of the first and second nanoribbons may mask the other of the first and second nanoribbons.

Abstract: An nucleic acid integrated detection method is provided, the method includes separating a lysis solution, a cleaning solution and a reaction solution in a detection reagent tube by providing a plurality of separation plugs in an over-under arrangement and disposing a hydrophobic layer in liquid or solid phase on each separation plug; adding a sample into the lysis solution; extracting nucleic acid in the sample using magnetic nanobeads; and then driving the magnetic nanobeads carrying the nucleic acid to sequentially pass through each hydrophobic layer along a magnetic bead channel and into the cleaning solution and the reaction solution to realize a cleaning and amplification for the nucleic acid, and finally, detecting the nucleic acid of the sample by an external device using an optical detection method, thus realizing a plurality of steps of nucleic acid extraction, cleaning and amplification reactions in the same detection reagent tube.

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Contact over active gate (COAG) structures with widened and lower capacitance gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using widened and lower capacitance gate insulating cap layers, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is coupled to the vertical stack of horizontal nanowires or the fin. A gate stack is over the vertical stack of horizontal nanowires or the fin, the gate stack including a gate dielectric and a gate electrode. A gate dielectric spacer is along sides of the gate stack. A gate insulating cap structure is on the gate stack and extending laterally beyond the gate stack, the gate insulating cap structure vertically over the gate dielectric spacer, and the gate insulating cap structure including a dielectric liner and a dielectric fill.

Abstract: Integrated circuit structures having backside isolation structures are described. An integrated circuit structure includes a first stack of nanowires or fin above a backside surface. A second stack of nanowires or fin is above the backside surface and is laterally spaced apart from the first stack of nanowires or fin. A gate electrode is around the first and second stacks of nanowires or fins. A first epitaxial source or drain structure is at an end of the first stack of nanowires or fin and at a side of the gate electrode. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin and at the side of the gate electrode. A dielectric structure extends from the backside surface into the gate electrode and laterally between the first epitaxial source or drain structure and the second epitaxial source or drain structure.

Abstract: An nucleic acid integrated detection reagent tube is provided, it includes a main tube and one or more branch tubes, wherein a lysing zone, a cleaning zone and a plurality of separation plugs comprising at least a least a separation plug and a second separation plug which are sequentially disposed, the first separation plug is used for separating the lysing zone and the cleaning zone, a reaction zone is provided in the branch tubes and the second separation plug is positioned at a connection between the branch tubes and the main tube or inside the branch tubes; hydrophobic layers in a liquid or a solid phase disposed at each of the plurality of separation plugs; and a magnetic bead channel for magnetically carrying the nucleic acid to sequentially pass through each hydrophobic layer penetrating to the branch tubes defined in an inner wall of the detection reagent tube.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Integrated circuit structures having metal gate cut plug structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure includes silicon and oxygen, with oxygen in direct contact with a metal-containing layer of the gate electrode.

Abstract: A method for detecting an infrared ship target based on an improved YOLOv7 is provided, including the following steps: obtaining an infrared maritime ship data set; reforming a YOLOv7 network structure based on an MobileNetv3 network and a bidirectional weighted feature pyramid network, and obtaining an infrared ship target detection model by introducing an attention mechanism and an optimized loss function; training and verifying the infrared ship target detection model based on the infrared maritime ship data set to obtain the infrared ship target detection model trained; and detecting a maritime ship based on the infrared ship target detection model trained.

Abstract: A method for screening a key stratum for overburden separation grouting in a coal mine includes: selecting overall analysis objects based on coal mine planning; conducting a primary screening of the analysis objects based on a scope of a subsidence zone; conducting a secondary screening of the analysis objects based on whether there is an old goaf; determining key stratums for screened-in analysis objects, prioritizing the key stratums based on a number of separation spaces and a range of a separation height, setting a safe height based on a diversion fissure zone, and prioritizing numbers of groutable layers based on a potential separation space and a water resistance of a rock stratum; prioritizing the groutable layers based on a fault impact; and comprehensively analyzing grouting priority levels of the key stratums based on results of the three prioritizations, and grouting separation layers of the key stratums in order of priority.

Abstract: The present invention belongs to the field of power system operations and provides a method for quantifying the flexibility demand and coordinating optimization of a hydro-wind-solar multi-energy complementary system. Firstly, the flexibility demand quantification method considering the uncertainty of wind and solar power output is constructed, and the wind and solar power output interval is divided by using quantile points to generate a set of output scenarios, and then the flexibility demand under each scenario is calculated. Based on the quantitative index of flexibility demand, an optimal operation model of hydro-wind-solar complementary system considering the minimum expectation of system flexibility deficiency is constructed to realize the optimal calculation of hydro-wind-solar complementary. By utilizing an actual wind-hydro complementary system of the Yunnan Power Grid, the model is validated for different new energy access ratios.