Patents by Inventor LinLin Chen

LinLin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11926098
    Abstract: A wire feeding mechanism suitable for fused deposition Additive Manufacturing (AM) of a flexible wire is provided, which includes a support housing. A melting nozzle is arranged at the lower end of the support housing, a hook is connected to the inner wall of the top end of the support housing, a connecting rod is connected to the inner wall of one side of the support housing, a wire drawing mechanism is connected to one end of the connecting rod, the wire drawing mechanism is located at the lower end of the hook, a limiting mechanism and a wire guide mechanism are connected to the inner wall of one side of the support housing, the limiting mechanism is located at the lower end of the wire drawing mechanism, the wire guide mechanism is located at the lower end of the limiting mechanism.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: March 12, 2024
    Assignee: NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS
    Inventors: Zhongde Shan, Congze Fan, Wenzhe Song, Yiwei Chen, Jinghua Zheng, Linlin Luo
  • Patent number: 11236094
    Abstract: Provided is a FGFR inhibitor, designating a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. Also provided is the application of a drug for treating solid tumors, such as FGFR related diseases.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: February 1, 2022
    Assignee: CSPC ZHONGQI PHARMACEUTICALL TECHNOLOGY (SHIJIAZHUANG) CO., LTD.
    Inventors: Yikai Wang, Yang Zhang, Zhengxia Chen, Linlin Chen, Tao Feng, Rongxin Huang, Qiu Li, Deyao Li, Jikui Sun, Yangyang Xu, Jie Li, Jian Li, Shuhui Chen
  • Publication number: 20210348217
    Abstract: The invention, in some aspects, includes systems, methods and components of molecular recorders that encode the timing of transcriptional activity into the sequence of RNA, which can then enable a sequencing-based readout of the internal dynamics of cells.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 11, 2021
    Inventors: Samuel Gordon RODRIQUES, Edward BOYDEN, Fei CHEN, Linlin CHEN, Sophia LIU, Ellen ZHONG, Joseph SCHERRER
  • Patent number: 11130761
    Abstract: Disclosed are an FGFR inhibitor and the use thereof in the preparation of a drug for treating FGFR-related diseases. In particular, disclosed are a compound as shown in formula (I) and a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 28, 2021
    Assignee: CSPC ZHONGQI PHARMACEUTICAL TECHNOLOGY (SHIJIAZHUANG) CO., LTD.
    Inventors: Yang Zhang, Yikai Wang, Linlin Chen, Tao Feng, Guoping Hu, Jian Li, Shuhui Chen
  • Publication number: 20210130357
    Abstract: Disclosed are an FGFR inhibitor and the use thereof in the preparation of a drug for treating FGFR-related diseases. In particular, disclosed are a compound as shown in formula (I) and a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 6, 2021
    Inventors: Yang ZHANG, Yikai WANG, Linlin CHEN, Tao FENG, Guoping HU, Jian LI, Shuhui CHEN
  • Publication number: 20200207773
    Abstract: Provided is a FGFR inhibitor, designating a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. Also provided is the application of a drug for treating solid tumors, such as FGFR related diseases.
    Type: Application
    Filed: August 15, 2018
    Publication date: July 2, 2020
    Inventors: Yikai WANG, Yang ZHANG, Zhengxia CHEN, Linlin CHEN, Tao FENG, Rongxin HUANG, Qiu LI, Deyao LI, Jikui SUN, Yangyang XU, Jie LI, Jian LI, Shuhui CHEN
  • Publication number: 20140151913
    Abstract: In one aspect the disclosure is directed to a method for inexpensively producing a Y2O3 nano-powder material, thereby facilitating the increased utilization of the material in different commercial application. In another aspect the disclosure is directed to Y2O3 nano-powder composite materials consisting of Y2O3 and at least one oxide selected from the group consisting of MgO, CaO, BeO2, Al2O3, TiO2, ZrO2, SiO2, HfO2, YbO2, GdO2, Lu2O3 and additional rare earth oxides.
    Type: Application
    Filed: November 4, 2013
    Publication date: June 5, 2014
    Applicant: CORNING INCORPORATED
    Inventors: Johnny Glen Arroyo, LinLin Chen, Weiguo Miao
  • Publication number: 20100116671
    Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Application
    Filed: October 3, 2006
    Publication date: May 13, 2010
    Applicant: Semitool, Inc.
    Inventors: Linlin Chen, Gregory J. Wilson, Paul R. McHugh, Robert A. Weaver, Thomas L. Ritzdorf
  • Patent number: 7462269
    Abstract: A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: December 9, 2008
    Assignee: Semitool, Inc.
    Inventors: Thomas L. Ritzdorf, E. Henry Stevens, LinLin Chen, Lyndon W. Graham, Curt Dundas
  • Publication number: 20080153393
    Abstract: A method for serially polishing a plurality of semiconductor wafers, wherein a CMP apparatus having a first polishing pad and a second polishing pad is provided. A first slurry composition is disposed between the first polishing pad and a first wafer when the first wafer is in a first state, and a first polishing on the first wafer via the first polishing pad and first slurry composition is commenced at a first commencement time. A second slurry composition is disposed between the second polishing pad and a second wafer when the second wafer is in a second state, and a second polishing on the second wafer via the second polishing pad and second slurry is commenced at a second commencement time, wherein the second commencement time differs from the first commencement time by a first intermediate period. One or more of the first wafer and the second wafer is rinsed with a pre-rinse agent for at least a portion of the first intermediate period.
    Type: Application
    Filed: March 12, 2007
    Publication date: June 26, 2008
    Inventors: Linlin Chen, Li Chen, Satyavolu Srinivas Papa Rao
  • Patent number: 7332066
    Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: February 19, 2008
    Assignee: Semitool, Inc.
    Inventors: Linlin Chen, Gregory J. Wilson, Paul R. McHugh, Robert A. Weaver, Thomas L. Ritzdorf
  • Patent number: 7198705
    Abstract: An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer (116). The surface of the first portion of the copper film (118) is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film (118) is electrochemically deposited.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: April 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Linlin Chen, Jiong-Ping Lu, Changfeng Xia
  • Patent number: 7144805
    Abstract: Methods for depositing a metal into a micro-recessed structure in the surface of a microelectronic workpiece are disclosed. The methods are suitable for use in connection with additive free as well as additive containing electroplating solutions. In accordance with one embodiment, the method includes making contact between the surface of the microelectronic workpiece and an electroplating solution in an electroplating cell that includes a cathode formed by the surface of the microelectronic workpiece and an anode disposed in electrical contact with the electroplating solution. Next, an initial film of the metal is deposited into the micro-recessed structure using at least a first electroplating waveform having a first current density. The first current density of the first electroplating waveform is provided to enhance the deposition of the metal at a bottom of the micro-recessed structure.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: December 5, 2006
    Assignee: Semitool, Inc.
    Inventors: LinLin Chen, Lyndon W. Graham, Thomas L. Ritzdorf, Dakin Fulton, Robert W. Batz, Jr.
  • Patent number: 7135404
    Abstract: The present invention is directed to a process for producing structures containing metallized features for use in microelectric workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and the metallized features according to the invention include an acid treatment of the barrier layer, an electrolytic treatment of the barrier layer, or deposition of a bonding layer between the barrier layer and metallized feature. The present invention thus modifies an exterior surface of a barrier layer making it more suitable for electrodeposition of metal on a barrier, thus eliminating the need for a PVD or CVD seed layer deposition process.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 14, 2006
    Assignee: Semitool, Inc.
    Inventors: Rajesh Baskaran, Bioh Kim, Linlin Chen, Lyndon W Graham
  • Patent number: 7115196
    Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: October 3, 2006
    Assignee: Semitool, Inc.
    Inventors: Linlin Chen, Gregory J. Wilson, Paul R. McHugh, Robert A. Weaver, Thomas L. Ritzdorf
  • Patent number: 7067015
    Abstract: A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment of the present invention, a cleaning chemistry comprising nitric acid, hydrofluoric acid, and phosphoric acid in solution with deionized water is applied to the wafer surface to be cleaned preferably while subjected to megasonic assist cleaning. The wafer is preferably then subjected to brush scrubbing and a deionized water rinse with megasonic assist cleaning.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Changfeng Xia, Linlin Chen
  • Patent number: 7048841
    Abstract: Contact assemblies, electroplating machines with contact assemblies, and methods for making contact assemblies that are used in the fabrication of microelectronic workpieces. The contact assemblies can be wet-contact assemblies or dry-contact assemblies. A contact assembly for use in an electroplating system can comprise a support member and a contact system coupled to the support member. The support member, for example, can be a ring or another structure that has an inner wall defining an opening configured to allow the workpiece to move through the support member along an access path. In one embodiment, the support member is a conductive ring having a plurality of posts depending from the ring that are spaced apart from one another by gaps. The contact system can be coupled to the posts of the support member. The contact system can have a plurality of contact members projecting inwardly into the opening relative to the support member and transversely with respect to the access path.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: May 23, 2006
    Assignee: Semitool, Inc.
    Inventors: Robert W. Batz, Jr., John M. Pedersen, John L. Klocke, LinLin Chen
  • Publication number: 20060084264
    Abstract: The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to the invention include an acid treatment of the barrier layer, an electrolytic treatment of the barrier layer, or deposition of a bonding layer between the barrier layer and metallized feature. The present invention thus modifies an exterior surface of a barrier layer making it more suitable for electrodeposition of metal on a barrier, thus eliminating the need for a PVD or CVD seed layer deposition process.
    Type: Application
    Filed: November 23, 2005
    Publication date: April 20, 2006
    Applicant: Semitool, Inc.
    Inventors: Rajesh Baskaran, Bioh Kim, Linlin Chen, Lyndon Graham
  • Publication number: 20060079084
    Abstract: The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to the invention include an acid treatment of the barrier layer, an electrolytic treatment of the barrier layer, or deposition of a bonding layer between the barrier layer and metallized feature. The present invention thus modifies an exterior surface of a barrier layer making it more suitable for electrodeposition of metal on a barrier, thus eliminating the need for a PVD or CVD seed layer deposition process.
    Type: Application
    Filed: November 23, 2005
    Publication date: April 13, 2006
    Applicant: Semitool, Inc.
    Inventors: Rajesh Baskaran, Bioh Kim, Linlin Chen, Lyndon Graham
  • Patent number: D828342
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 11, 2018
    Assignee: SHENZHEN ZHIQU TECHNOLOGY LIMITED
    Inventor: Linlin Chen